Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1709 / 3738

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Display Subsystem Basic Programming Model
– Active matrix (TFT) display: DSS. DISPC_GFX_PRELOAD [11:0] PRELOAD = 0x60 (value is 96)
– Color passive matrix (STN) display: DSS. DISPC_GFX_PRELOAD [11:0] PRELOAD = 0x72 (value is
114)
– Monochrome passive matrix (STN) display: DSS. DISPC_GFX_PRELOAD [11:0] PRELOAD = 0xE0
(value is 224)
• Base address of the graphics buffer in system memory (DSS. DISPC_GFX_BAj registers): The default
value of these two registers at reset time is 0x0. The horizontal resolution is one pixel because the
base address is aligned on a pixel size boundary. In case of 4 BPP, the resolution is two pixels; for 2
BPP, resolution is four pixels; for 1 BPP, resolution is eight pixels; and for RGB24 packed format, the
resolution is four pixels. The vertical resolution is one line. The register DSS.DISPC_GFX_BA0 defines
the base address of the even field; and DSS.DISPC_GFX_BA1 defines the base of the odd field in the
case of an external synchronization and based on the value of the input signal DISPC_FID and the
polarity. To improve system throughput, the base address should be aligned on the burst size
boundary.
• Graphics FIFO threshold (DSS. DISPC_GFX_FIFO_THRESHOLD register): The low threshold
(DSS. DISPC_GFX_FIFO_THRESHOLD [11:0] GFXFIFOLOWTHRESHOLD) and the high threshold
(DSS. DISPC_GFX_FIFO_THRESHOLD [27:16] GFXFIFOHIGHTHRESHOLD) values define the FIFO
DMA behavior. When the low level is reached, one or more requests are issued to the L3-based
interconnect to fill up the FIFO to reach the high threshold. A request is issued as long as the FIFO
has enough space available to accept a burst. The DMA engine then waits until the low level is
reached to restart the requests. By setting the DSS.
DISPC_CONFIG [14] FIFOMERGE bit to 1, users
merge the three FIFOs (GFX, VID1, and VID2). In this case, the low threshold (the
DSS.
DISPC_GFX_FIFO_THRESHOLD [11:0] GFXFIFOLOWTHRESHOLD bit field) and the high
threshold (DSS. DISPC_GFX_FIFO_THRESHOLD [27:16] GFXFIFOHIGHTHRESHOLD bit field) values
must be programmed with a multiplier factor of three (3 x value). By default, the FIFOs are not merged
(the DSS.
DISPC_CONFIG [14] FIFOMERGE bit reset value is 0).
• Palette/gamma table used (DSS. DISPC_CONFIG [3] PALETTEGAMMATABLE bit): The bit indicates if
the palette must be loaded before the graphics data for the following frame. The bit is set by software
and reset by hardware.
• Base address of the palette/gamma table buffer in system memory (DSS. DISPC_GFX_TABLE_BA
register): The default value of this register at reset time is 0x0. The base address is aligned on a 32-bit
address. Depending on the pixel size of graphics data (1, 2, 4, or 8 BPP), 16 (1, 2, or 4 BPP), or 256
(8 BPP) x 32-bit values are loaded from system memory into the internal table memory. To load the
table when using the memory as a gamma table, the graphics pipeline is enabled and then disabled by
the software when the palette loaded interrupt is generated. The overlay manager ignores the graphics
pipe when the table is used as a gamma table.
NOTE: In case of RGB16 format and optimization enabled, the base address is aligned on a 32-bit
boundary and the number of bytes to skip is a multiple of 4 bytes.
• Graphics Priority (DSS. DISPC_GFX_ATTRIBUTES [14] GFXARBITRATION): The default value at reset
time is 0x0. It is used to change between normal priority (value of 0) to high priority (value of 1) to
change priority for the graphics channel vs. video channels. It can be used to give higher priority to the
pipelines with real time constraint vs. non real time pipelines. For that is, pipelines associated to the
LCD output in RFBI mode should have lower priority than pipelines associated to TV output.
• Graphics Self-Refresh (DSS. DISPC_GFX_ATTRIBUTES [15] GFXSELFREFRESH): The default value
at reset time is 0x0. It is used to use the DMA FIFO without accessing the interconnect for multiple
frames. Once, the data have been loaded to the DMA FIFO for displaying the frame, they are used for
the following frames.
The sequence to activate the self-refresh is the following:
– Frame t: The bit field should be set at anytime during frame
– Frame t+1: Fetch of the data in the DMA FIFO and display of the frame
– Frame t+2: No access to the L3 interconnect, DMA FIFO uses to provide the pixels
The sequence to deactivate the self-refresh is the following:
– Frame t: No access to the L3 interconnect, DMA FIFO uses to provide the pixels, bit field can be
changed at any time during the frame
– Frame t+1: Fetch of the data from system memory using the L3 interconnect
1709 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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