Public Version
www.ti.com
Display Subsystem Register Manual
Table 7-181. Register Call Summary for Register DISPC_GFX_ATTRIBUTES
Display Subsystem Functional Description
•
:
Display Subsystem Basic Programming Model
•
Display Controller Basic Programming Model
:
•
•
Graphics Layer Configuration Registers
:
•
:
•
:
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
•
Table 7-182. DISPC_GFX_FIFO_THRESHOLD
Address Offset
0x0A4
Physical address
0x4805 04A4
Instance
DISC
Description
The register configures the graphics FIFO.
Shadow register, updated on VFP start period or EVSYNC.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
GFXFIFOHIGHTHRESHOLD
Reserved
GFXFIFOLOWTHRESHOLD
Bits
Field Name
Description
Type
Reset
31:28
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0x00
27:16
GFXFIFOHIGH
Graphics FIFO High Threshold
RW
0x3FF
THRESHOLD
Number of bytes defining the threshold value.
15:12
Reserved
Write 0s for future compatibility. Read returns 0
RW
0x00
11:0
GFXFIFOLOW
Graphics FIFO Low Threshold
RW
0x3C0
THRESHOLD
Number of bytes defining the threshold value
Table 7-183. Register Call Summary for Register DISPC_GFX_FIFO_THRESHOLD
Display Subsystem Basic Programming Model
•
Display Controller Basic Programming Model
:
•
•
:
Display Subsystem Use Cases and Tips
•
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
Table 7-184. DISPC_GFX_FIFO_SIZE_STATUS
Address Offset
0x0A8
Physical address
0x4805 04A8
Instance
DISC
Description
This register defines the graphics FIFO size.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
GFXFIFOSIZE
1847
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated