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Display Subsystem Basic Programming Model
NOTE:
When the RGB24 packet format is selected, the valid values are 1 and any value multiples
of 12 bytes (4x32 bit). When the value is a multiple of 12 bytes, the width must be a multiple
of 12 bytes. When the value is 1, the width can be any size from 1 to 2048 pixels.
•
DSS.DISPC_xxx_ATTRIBUTES: These registers contain the main settings for the pipeline, such as the
image data format, the rotation value, and the enable bit for the pipeline. The bit fields of these
registers play a role in the rotation and in the image data format setup.
–
The following bit fields are used by the graphics pipeline to set up the image format:
•
GFXENABLE: Set this field to activate the hardware path in use.
•
GFXFORMAT: Use this field to specify the format of the graphic frame.
•
GFXROTATION: Set this field to the value corresponding to the rotation angle desired only if the
frame contains RGB24 pixel data; otherwise, set it to 0x0 regardless of the degree of rotation.
•
GFXREPLICATIONENABLE: Use this bit to determine whether the encoded pixel data in RGB
formats (RGB12 and RGB16) is extended to 24-bit format with or without replication of the MSB
to fill the LSBs of each color component. If the replication logic is turned off, the LSB parts are
filled with 0s. It is recommended to always enable this feature.
•
GFXCHANNELOUT: Set this field based on whether the frame is to be rendered on the LCD or
on the TV set.
–
The following bit fields for the two video pipelines:
•
VIDENABLE: Set this field to activate the hardware path in use.
•
VIDFORMAT: Use this field to specify the format of the video frame (RGB16 or YUV4:2:2).
•
VIDCOLORCONVENABLE: If the video is in YUV4:2:2 format, set this field to enabled.
•
VIDROTATION: Set this field to the value corresponding to the rotation angle desired only if the
frame contains non-RGB pixel data; otherwise, set it to 0x0 regardless of the degree of rotation.
See
for more information.
•
VIDROWREPEATENABLE: Set this field to enabled only if the frame contains YUV pixel data
and the rotation is 90-degree or 270-degree so that the row pixel data are fetched twice to
extract both Y components. See
for more information.
•
VIDCHANNELOUT: Set this field based on whether the frame is to be rendered on the LCD or
on the TV set.
•
DSS.DISPC_xxx_POSITION: Use this register to configure the position of the window.
•
DSS.DISPC_xxx_SIZE: Use this register to configure the size of the window.
•
DSS.
, DSS.
,
DSS.
, DSS.
, and
DSS.
: These registers contain the conversion coefficients required for
YUV-to-RGB color conversion.
•
DSS.DISPC_xxx_FIFO_THRESHOLD: Set the low threshold
(DSS.
[11:0] GFXFIFOLOWTHRESHOLD) and the high threshold
(DSS.
[27:16] GFXFIFOHIGHTHRESHOLD) values to define the
FIFO DMA behavior. When the low level is reached, one or more requests are issued to the L3-based
interconnect to fill up the FIFO to reach the high threshold. The DMA engine then waits until the low
level is reached to restart the requests.
7.5.3.4.2.2 DMA Register Settings
To configure the display controller for rotation and/or mirroring, use the following settings:
1721
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated