Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-118. Display Controller Register Mapping Summary (continued)
Register Name Type Register Width Address Offset Physical Address
(Bits)
DISPC_GLOBAL_ALPHA RW 32 0x074 0x4805 0474
DISPC_SIZE_DIG RW 32 0x078 0x4805 0478
DISPC_SIZE_LCD RW 32 0x07C 0x4805 047C
DISPC_GFX_BAj RW 32 0x080+(j * 0x04)
(2)
0x4805 0480+(j * 0x04)
(2)
DISPC_GFX_POSITION RW 32 0x088 0x4805 0488
DISPC_GFX_SIZE RW 32 0x08C 0x4805 048C
DISPC_GFX_ATTRIBUTES RW 32 0x0A0 0x4805 04A0
DISPC_GFX_FIFO_THRESHOLD RW 32 0x0A4 0x4805 04A4
DISPC_GFX_FIFO_SIZE_STATUS R 32 0x0A8 0x4805 04A8
DISPC_GFX_ROW_INC RW 32 0x0AC 0x4805 04AC
DISPC_GFX_PIXEL_INC RW 32 0x0B0 0x4805 04B0
DISPC_GFX_WINDOW_SKIP RW 32 0x0B4 0x4805 04B4
DISPC_GFX_TABLE_BA RW 32 0x0B8 0x4805 04B8
DISPC_DATA_CYCLEk RW 32 0x1D4+(k * 0x04)
(3)
0x4805 05D4+(k *
0x04)
(3)
DISPC_CPR_COEF_R RW 32 0x220 0x4805 0620
DISPC_CPR_COEF_G RW 32 0x224 0x4805 0624
DISPC_CPR_COEF_B RW 32 0x228 0x4805 0628
DISPC_GFX_PRELOAD RW 32 0x22C 0x4805 062C
(2)
j = 0 to 1
(3)
k = 0 to 2
7.7.1.3 Display Controller VID1 Register Mapping Summary
Table 7-119. Display Controller VID1 Register Mapping Summary
Register Name (n=1 for VID1) Type Register Width Address Offset Display controller VID1
(Bits) Physical
Address
DISPC_VIDn_BAj RW 32 0x0BC+((n–1)* 0x90) + 0x4805 04BC + (j
(j * 0x04)
(1)
*0x04)
(1)
DISPC_VIDn_POSITION RW 32 0x0C4+((n–1)* 0x90) 0x4805 04C4
DISPC_VIDn_SIZE RW 32 0x0C8+((n–1)* 0x90) 0x4805 04C8
DISPC_VIDn_ATTRIBUTES RW 32 0x0CC+((n–1)* 0x90) 0x4805 04CC
DISPC_VIDn_FIFO_THRESHOLD RW 32 0x0D0+((n–1)* 0x90) 0x4805 04D0
DISPC_VIDn_FIFO_SIZE_STATUS R 32 0x0D4+((n–1)* 0x90) 0x4805 04D4
DISPC_VIDn_ROW_INC RW 32 0x0D8+((n–1)* 0x90) 0x4805 04D8
DISPC_VIDn_PIXEL_INC RW 32 0x0DC+((n–1)* 0x90) 0x4805 04DC
DISPC_VIDn_FIR RW 32 0x0E0+((n–1)* 0x90) 0x4805 04E0
DISPC_VIDn_PICTURE_SIZE RW 32 0x0E4+((n–1)* 0x90) 0x4805 04E4
DISPC_VIDn_ACCUl RW 32 0x0E8 + ((n–1)* 0x90) 0x4805 04E8 + (l* 0x04)
(2)
+ (l* 0x04)
(2)
DISPC_VIDn_FIR_COEF_Hi RW 32 0x0F0+ ((n–1)* 0x90) + 0x4805 04F0+ (i* 0x08)
(3)
(i* 0x08)
(3)
DISPC_VIDn_FIR_COEF_HVi RW 32 0x0F4+ ((n–1)* 0x90) + 0x4805 04F4 + (i*0x08)
(3)
(i* 0x08)
(3)
DISPC_VIDn_CONV_COEF0 RW 32 0x130+((n–1)* 0x90) 0x4805 0530
DISPC_VIDn_CONV_COEF1 RW 32 0x134+((n–1)* 0x90) 0x4805 0534
(1)
j = 0 to 1
(2)
l = 0 to 1
(3)
i = 0 to 7
1813 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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