Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1856 / 3738

Public Version
Display Subsystem Register Manual
www.ti.com
Table 7-204. DISPC_VIDn_FIFO_SIZE_STATUS
Address Offset 0x0D4+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2
Physical address 0x4805 04D4+((–1)* 0x90) Instance DISC
Description The register defines the video FIFO size for video pipeline #n.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved VIDFIFOSIZE
Bits Field Name Description Type Reset
31:11 Reserved Write 0s for future compatibility. Read returns 0. R 0x000000
10:0 VIDFIFOSIZE Video FIFO Size R 0x400
Number of bytes defining the FIFO value
Table 7-205. Register Call Summary for Register DISPC_VIDn_FIFO_SIZE_STATUS
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [0]
• Display Controller VID2 Register Mapping Summary : [1]
Table 7-206. DISPC_VIDn_ROW_INC
Address Offset 0x0D8+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2
Physical address 0x4805 04D8+ ((–1)* 0x90) Instance DISC
Description The register configures the number of bytes to increment at the end of the row for the buffer associated with video
window #n.
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VIDROWINC
Bits Field Name Description Type Reset
31:0 VIDROWINC Number of bytes to increment at the end of the row RW 0x00000001
Encoded signed value (from -2
31
- 1 to 2
31
) to specify the number of bytes to
increment at the end of the row in the video buffer.
The value 0 is invalid. The value 1 means next pixel. The value 1+n*BPP
means increment of n pixels. The value 1- (n+1)*BPP means decrement of
n pixels.
Table 7-207. Register Call Summary for Register DISPC_VIDn_ROW_INC
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Video DMA Registers : [1]
• Video Window Attributes : [2] [3]
• Rotation/Mirroring Registers : [4]
• DMA Register Settings : [5] [6]
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [7]
• Display Controller VID2 Register Mapping Summary : [8]
1856 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated