Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1715 / 3738

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Display Subsystem Basic Programming Model
• Video format (DSS. DISPC_VIDn_ATTRIBUTES [4:1] VIDFORMAT bit field, with n = 1 or 2): The default
value at reset time is 0x0 (BITMAP 1 BPP, nonsupported format by the video pipeline).The video
format can be RGB16, RGB24, YUV2 4:2:2 co-DSS sited, and UYVY 4:2:2 co-sited.
• Video window X-position (DSS. DISPC_VIDn_POSITION [10:0] VIDPOSX bit field, with n = 1 or 2): The
default value at reset time is 0x0 (first column starting on the left edge of the screen). The window
X-position is from 0 to 2047 columns. All integer values in the range [0:2047] are allowed.
• Video window Y-position (DSS. DISPC_VIDn_POSITION [26:16] VIDPOSY bit field, with n = 1 or 2):
The default value at reset time is 0x0 (first row starting at the top of the screen). The window Y-position
is from 0 to 2047 rows. All integer values in the range [0:2047] are allowed.
• Video window width (DSS. DISPC_VIDn_SIZE [10:0] VIDSIZEX bit field, with n = 1 or 2): The default
value at reset time is 0x0 (1 pixel). The window width is from 1 to 2048 pixels. All integer values in the
range [1:2048] are allowed. The maximum bandwidth efficiency for accessing the pixels in system
memory is reached when the width (in bytes) of the video window is a multiple of the video burst size
defined in the DSS.
DISPC_VIDn_ATTRIBUTES [15:14] VIDBURSTSIZE bit field (in bytes).
NOTE: When the RGB24 packed format is selected, the width must be a multiple of 12 bytes when
the DSS. DISPC_VIDn_ROW_INC register is not 1. When the DSS. DISPC_VIDn_ROW_INC
register is 1, the width can be any size from 1 to 2048 pixels.
The entire pixels of the video window must be inside the LCD screen. Depending on the
width of the buffer to be displayed in the video layer and the position, the width should be
adjusted by software to limit the right edge of the window inside the screen.
• Video window height (DSS. DISPC_VIDn_SIZE [26:16] VIDSIZEY bit field, with n = 1 or 2): The default
value at reset time is 0x0 (1 pixel). The window height is from 1 to 2048 pixels. All integer values in the
range [1:2048] are allowed. The entire pixels of the video window must be inside the LCD screen.
Depending on the height of the buffer to be displayed in the video layer and the position, the height
should be adjusted by software to limit the bottom edge of the window inside the screen.
• Video picture width in system memory (DSS. DISPC_VIDn_PICTURE_SIZE [10:0] VIDORGSIZEX bit
field, with n = 1 or 2): The default value at reset time is 0x0 (1 pixel). The window width is from 1 to
2048 pixels. All integer values in the range [1:2048] are allowed with RGB16 and RGB24 video data.
For YUV2 4:2:2 and UYVY 4:2:2 formats, the width must be a multiple of two pixels. The maximum
bandwidth efficiency for accessing the pixels in system memory is reached when the width (in bytes) of
the video picture is a multiple of the video burst size defined in the
DSS.
DISPC_VIDn_ATTRIBUTES [15:14] VIDBURSTSIZE bit field (in bytes).
• Video picture height in system memory (the DSS. DISPC_VIDn_PICTURE_SIZE [26:16] VIDORGSIZEY
bit field, with n = 1 or 2): The default value at reset time is 0x0 (1 pixel). The window width is from 1 to
2048 pixels. All integer values in the range [1:2048] are allowed.
• Video Priority (DSS. DISPC_VIDn_ATTRIBUTES [23] VIDARBITRATION): The default value at reset
time is 0x0. It is used to change between normal priority (value of 0) to high priority (value of 1) to
change priority for the video channel vs. other channels. It can be used to give higher priority to the
pipelines with real time constraint vs. non real time pipelines. For that is, pipelines associated to the
LCD output in RFBI mode should have lower priority than pipelines associated to TV output.
• Video Self-Refresh (DSS. DISPC_VIDn_ATTRIBUTES [24] VIDSELFREFRESH): The default value at
reset time is 0x0. It is used to use the DMA FIFO without accessing the interconnect for multiple
frames. Once, the data have been loaded to the DMA FIFO for displaying the frame, they are used for
the following frames.
The sequence to activate the self-refresh is the following:
– Frame t: The bit field should be set at anytime during frame
– Frame t+1: Fetch of the data in the DMA FIFO and display of the frame
– Frame t+2: No access to the L3 interconnect, DMA FIFO uses to provide the pixels
The sequence to deactivate the self-refresh is the following:
– Frame t: No access to the L3 interconnect, DMA FIFO uses to provide the pixels, bit field can be
changed at any time during the frame
– Frame t+1: Fetch of the data from system memory using the L3 interconnect
1715 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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