Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
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Table 7-199. Register Call Summary for Register DISPC_VIDn_SIZE
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Video Configuration Register : [1]
• Video Window Attributes : [2] [3]
• Rotation/Mirroring Registers : [4]
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [5]
• Display Controller VID2 Register Mapping Summary : [6]
Table 7-200. DISPC_VIDn_ATTRIBUTES
Address Offset 0x0CC+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2
Physical address 0x4805 04CC+ ((–1)* 0x90) Instance DISC
Description The register configures the attributes of video window #n such as format, resizeenable, shadow register, updated
on VFP start period, or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VIDFORMAT
RESERVED RESERVED
VIDENABLE
VIDROTATION
VIDBURSTSIZE
VIDFULLRANGE
VIDENDIANNESS
VIDARBITRATION
VIDCHANNELOUT
VIDFIFOPRELOAD
VIDVRESIZECONF
VIDHRESIZECONF
VIDSELFREFRESH
VIDVERTICALTAPS VIDRESIZEENABLE
PREMULTIPLYALPHA
VIDLINEBUFFERSPLIT
VIDDMAOPTIMIZATION
VIDROWREPEATENABLE VIDCOLORCONVENABLE
VIDREPLICATIONENABLE
Bits Field Name Description Type Reset
31: 29 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0000
28 PREMULTIPLYALPHA The field configures the DISPC VID2 to process incoming data as RW 0
pre-multiplied alpha data or non pre-multiplied alpha data.
Default setting is non pre-multiplied alpha data.
0x0: Non pre-multiplyalpha data color component
0x1: Premultiplyalpha data color component
NOTE: The pre-multiplied alpha control is
supported only on VID2.
For VID1 this bitfield is
RESERVED.
The pre-multiplied alpha option is
only valid when bit field [4:1]
VIDFORMAT is set to ARGB or
RGBA formats. Otherwise, the
PREMULTIPLYALPHA bit field is
ignored by the hardware.
27: 25 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0000
24 VIDSELFREFRESH Enables the self refresh of the video window from its own FIFO RW 0
only.
0x0: The video pipeline accesses the interconnect to fetch data
from the system memory
0x1: The video pipeline does not need anymore to fetch data
from memory. Only the video FIFO is used. It takes effect
after the frame has been loaded in the FIFO
1852 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated