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Display Subsystem Basic Programming Model
In the case of the digital output, after programming the shadow registers, the DSS.
GODIGITAL bit must be set to 1. If this bit is not set, the configuration of the display controller will have no
effect. This setting indicates that all display controller shadow registers are programmed and that
hardware can update the internal registers at the external EVSYNC.
In the case of the LCD output, after programming the shadow registers, the DSS.
GOLCD bit must be set to 1. If this bit is not set, the configuration of the display controller will have no
effect. This setting indicates that all display controller shadow registers are programmed and that
hardware can update the internal registers at the VFP start period.
Before setting either the DSS.
[5] GOLCD or DSS.
[6] GODIGITAL
bit, ensure that the bit is cleared.
lists the shadow registers.
Table 7-47. Shadow Registers
Shadow Register Name
Updated on VFP Start Period
Updated on External VSYNC
(LCD output)
(Digital output)
DSS.
X
(1)
X
(1)
DSS.
X
X
DSS.
(m = 0)
X
DSS.
(m = 1)
X
DSS.
(m = 0)
X
DSS.
(m = 1)
X
DSS.
X
DSS.
X
DSS.
X
DSS.
X
DSS.
X
DSS.
X
DSS.
X
DSS.
(j = 0,1)
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
DSS.
X
DSS.
X
DSS.
(j= 0,1)
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
DSS.
X
X
(1)
Some of the register bit fields are shadow bits. For more information, see
, Display Subsystem Register Manual.
1707
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated