Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1855 / 3738

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Display Subsystem Register Manual
Table 7-201. Register Call Summary for Register DISPC_VIDn_ATTRIBUTES
Display Subsystem Functional Description
• Up-/Down-Sampling : [0]
• Overlay Support : [1]
• Priority Rule : [2] [3]
• Rotation : [4]
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [5]
• Video DMA Registers : [6] [7] [8] [9] [10] [11]
• Video Configuration Register : [12] [13]
• Video Window Attributes : [14] [15] [16] [17] [18]
• Video Up-/Down-Sampling Configuration : [19] [20] [21] [22] [23] [24] [25]
• Rotation/Mirroring Registers : [26]
• Additional Configuration When Using YUV Format : [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43]
[44]
• Video DMA Optimization : [45] [46] [47] [48] [49] [50] [51] [52] [53]
Display Subsystem Use Cases and Tips
• Vertical Filtering : [54]
• Register List : [55]
• Enabling : [56] [57]
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [58]
• Display Controller VID2 Register Mapping Summary : [59]
• Display Controller Registers : [60]
Table 7-202. DISPC_VIDn_FIFO_THRESHOLD
Address Offset 0x0D0+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2
Physical address 0x4805 04D0+ ((–1)* 0x90) Instance DISC
Description The register configures the video FIFO associated with video pipeline #n.
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved VIDFIFOHIGHTHRESHOLD Reserved VIDFIFOLOWTHRESHOLD
Bits Field Name Description Type Reset
31:28 Reserved Write 0s for future compatibility. Read returns 0. RW 0x00
27:16 VIDFIFOHIGH Video FIFO high threshold RW 0x3FF
THRESHOLD Number of bytes defining the threshold value
15:12 Reserved Write 0s for future compatibility. Read returns 0. RW 0x00
11:0 VIDFIFOLOW Video FIFO low threshold RW 0x3C0
THRESHOLD Number of bytes defining the threshold value
Table 7-203. Register Call Summary for Register DISPC_VIDn_FIFO_THRESHOLD
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Video DMA Registers : [1] [2] [3] [4] [5] [6]
• Rotation/Mirroring Registers : [7]
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [8]
• Display Controller VID2 Register Mapping Summary : [9]
1855 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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