Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1717 / 3738

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Display Subsystem Basic Programming Model
DSS. DISPC_VIDn_ATTRIBUTES [22] VIDLINEBUFFERSPLIT bit must be set to 1.
• Vertical up/downsampling line buffer configuration (DSS. DISPC_VIDn_ATTRIBUTES [20]
VIDDMAOPTIMIZATION bit): The default value at reset time is 0x0 (no optimization). If the bit is set,
the DMA engine fetches two pixels for each 32-bit OCP request (RGB16 and YUV4:2:2) while doing
90- and 270-degree rotation. If the bit is clear, the DMA engine fetches one pixel for each 32-bit OCP
request (RGB16 and YUV4:2:2) while doing 90- and 270-degree rotation. The width and height of
picture should be even to use the optimization. Even width is required for the input picture when the
5-tap configuration is used.
NOTE: If the 5-tap resizer is used for RGB16 and YUV4:2:2 picture formats, the width of the input
picture must be a multiple of 2 pixels and more than 5 pixels. This leads to the following
register configuration:
DISPC_VIDn_ATTRIBUTES [21] VIDVERTICALTAPS == 1
DISPC_VIDn_PICTURE_SIZE [10:0] VIDORGSIZEX > 4 and even
For more information about the configuration of video DMA optimization, see Section 7.5.3.4.5 , Video
DMA Optimization.
• Horizontal up/downsampling accumulator value (DSS. DISPC_VIDn_ACCUl [9:0]
VIDHORIZONTALACCU bit field): The unsigned integer value range is [0:1023]. The accumulator
value indicates in which phase the horizontal filtering starts. The value 0 indicates that 0 is the first
phase used by the hardware to generate the first data (see
Table 7-48 ).
Table 7-48. Vertical/Horizontal Accumulator Phase
Accumulator Value Phases f
0 0
128 1
256 2
384 3
512 4
640 5
768 6
896 7
• Vertical up/downsampling coefficients (DSS. DISPC_VIDn_FIR_COEF_HVi registers, with n = 1 or 2,
i = 0 to 7): The 3-tap vertical up/downsampling coefficients are defined in these registers. There are
eight registers for the eight phases with three coefficients for each, or a total of 24 programmable
coefficients for the vertical up/downsampling block. Each register contains two 8-bit signed coefficients
and one 8-bit unsigned coefficient (the central one).
In addition, there are 2-tap vertical up/downsampling coefficients defined in
DSS.
DISPC_VIDn_FIR_COEF_Vi registers. There are 8 registers for the 8 phases with 2 coefficients
for each of them so a total of 16 programmable coefficients for the vertical up/downsampling block
used in addition of the 3-tap registers defined above. Each register contains two 8-bit signed
coefficients. In case of 5-tap configuration, both sets of registers DSS.
DISPC_VIDn_FIR_COEF_HVi
and DSS. DISPC_VIDn_FIR_COEF_Vi are used. In case of 3-tap configuration, only one set of
registers DSS. DISPC_VIDn_FIR_COEF_HVi is used.
• Horizontal up/downsampling coefficients (DSS. DISPC_VIDn_FIR_COEF_Hi and
DISPC_VIDn_FIR_COEF_HVi registers, with n = 1 or 2, i = 0 to 7): The
DSS. DISPC_VIDn_FIR_COEF_Hi register and the DSS. DISPC_VIDn_FIR_COEF_HVi register define
the 5-tap horizontal up/downsampling coefficients. There are eight registers for the eight phases with
five coefficients for each register, or a total of 40 programmable coefficients for the horizontal
up/downsampling block.
Each DSS.
DISPC_VIDn_FIR_COEF_Hi register contains three 8-bit signed coefficients and one 8-bit
unsigned coefficient (the central one). Each DSS. DISPC_VIDn_FIR_COEF_HVi register contains one
8-bit signed coefficient.
The programmable coefficient for the FIR up/downsampling method must be adjusted based on
application needs. For more details on scaling programming settings, see
Section 7.6.1 .
1717 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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