Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Basic Programming Model
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Table 7-56. Video Rotation Register Settings (YUV Only) (continued)
Rotation Registers (with n = 1 or 2) SDRAM + Rotation
engine
270 degree DSS. DISPC_VIDn_ATTRIBUTES [13] VIDROTATION 0x3
DSS. DISPC_VIDn_ATTRIBUTES [18] VIDROWREPEATENABLE 0x1
Table 7-57. Video Rotation With Mirroring Register Settings (YUV only)
Rotation Registers (with n = 1 or 2) SDRAM + Rotation
engine
0 degree DSS. DISPC_VIDn_ATTRIBUTES [13] VIDROTATION 0x2
DSS. DISPC_VIDn_ATTRIBUTES [18] VIDROWREPEATENABLE 0x0
90 degrees DSS. DISPC_VIDn_ATTRIBUTES [13] VIDROTATION 0x1
DSS. DISPC_VIDn_ATTRIBUTES [18] VIDROWREPEATENABLE 0x1
180 degrees DSS. DISPC_VIDn_ATTRIBUTES [13] VIDROTATION 0x0
DSS. DISPC_VIDn_ATTRIBUTES [18] VIDROWREPEATENABLE 0x0
270 degree DSS. DISPC_VIDn_ATTRIBUTES [13] VIDROTATION 0x3
DSS. DISPC_VIDn_ATTRIBUTES [18] VIDROWREPEATENABLE 0x1
NOTE: For YUV4:2:2 video-encoded pixels, the hardware must always fetch a 32-bit value from the
system memory to generate a YUV4:4:4 value before YUV-to-RGB conversion.
• For 90- and 270-degree rotation, the missing chrominance samples for the odd pixels are generated by
duplicating the chrominance samples of the previous even pixels.
• For 0- and 180-degree rotation, the missing chrominance samples for the odd pixels are generated by
averaging the contiguous chrominance samples.
7.5.3.4.5 Video DMA Optimization
When a rotation of 90 or 270 degrees is required, the memory traffic can be reduced as described in
Section 7.4.2.8 , Rotation.
1. Enable DMA optimization for the video pipelines VID1 and VID2 by applying the following settings to
the DISPC:
(a) Enable DISPC DMA optimization by setting:
• DISPC_VIDn_ATTRIBUTES [20] VIDDMAOPTIMIZATION = 1
• DISPC_VIDn_ATTRIBUTES [18] VIDROWREPEATENABLE = 0
• DISPC_VIDn_ATTRIBUTES [13:12] VIDROTATION = 0x1 or 0x3
(b) Configure DISPC for the following format:
• DISPC_VIDn_ATTRIBUTES [4:1] VIDFORMAT = 0x6, 0xA, or 0xB
• DISPC_VIDn_ATTRIBUTES [9] VIDCOLORCONVENABLE = 0x1 (only for YUV format)
(c) Configure DISPC scaler in 5-tap mode by setting:
• DISPC_VIDn_ATTRIBUTES [21] VIDVERTICALTAPS = 0x1
• DISPC_VIDn_ATTRIBUTES [6:5] VIDRESIZEENABLE = 0x2 (vertical resize only, minimum
setting) or 0x3 (ve horizontal resize)
• DISPC_VIDn_ATTRIBUTES [22] VIDLINEBUFFERSPLIT = 0x1
2. Configure the rotation engine (VRFB) inside the SDRAM memory scheduler (SMS) as follows:
(a) Set the SMS-VRFB context pixel size to 32 bits by setting:
• For RGB16 pixel format:
– Writing context: SMS.SMS_ROT_CONTROLn[1:0] PS = 1
– Reading context: SMS.SMS_ROT_CONTROLn[1:0] PS = 2
• For YUV pixel format:
– Writing and reading context: SMS.SMS_ROT_CONTROLn[1:0] PS = 2
(b) Set the SMS-VRFB context width to one half of the original width:
1728 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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