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Display Subsystem Functional Description
Table 7-29. 8-Bit Interface Configuration/24-Bit Mode
24-Bit Mode
1st Cycle
2nd Cycle
3rd Cycle
Data[7]
R0[7]
G0[7]
B0[7]
Data[6]
R0[6]
G0[6]
B0[6]
Data[5]
R0[5]
G0[5]
B0[5]
Data[4]
R0[4]
G0[4]
B0[4]
Data[3]
R0[3]
G0[3]
B0[3]
Data[2]
R0[2]
G0[2]
B0[2]
Data[1]
R0[1]
G0[1]
B0[1]
Data[0]
R0[0]
G0[0]
B0[0]
7.4.2.6
Video Line Buffer
The line buffer size is 1024 x 24-bit. There are six line buffers (1024 x 24-bit) that can be merged into
three lines (2048 x 24-bit).
lists the maximum width depending on the TAP configuration and
the pixel format.
Table 7-30. Maximum Width Allowed
Vertical Tap
Pixel Format
Maximum Width (Pixels)
3
RGB16
2048
RGB24
YUV4:2:2
5
RGB16
1024
RGB24
YUV4:2:2
7.4.2.7
Synchronized Buffer Update
A synchronization mismatch between the frame buffer and the display refreshes, named tearing effect,
can lead to images that appear to be stretched on the screen. To avoid this, a synchronization mechanism
is needed between the display controller and the process that updates the buffer. An interrupt is generated
when the display reaches a predefined line number. This PROGRAMMEDLINENUMBER interrupt is a
level signal and stays active during the programmed line of the display.
7.4.2.8
Rotation
In case of SDRAM buffer, the display controller accesses the encoded pixels in burst, always considering
the consecutive data in memory. The rotation engine (VRFB) in the SDRAM scheduler (SDRC) is in
charge of translating the addresses from virtual to physical SDRAM addresses (see
, Memory
Subsystem).
Rotation using the SMS-VRFB rotation engine is supported for BITMAP8, RGB12 (16-bit container),
ARGB16, RGB16, RGB24 (using 32-bit container), ARGB32, RGBA32, and YUV4:2:2 (YUV2 and YUYV).
The BITMAP1, BITMAP2, BITMAP4, and RGB24 (using 24-bit container) formats are not supported.
NOTE:
For good performance in the L3 interconnect and for SDRAM efficiency, it is highly
recommended to use the VRFB rotation engine when possible and not the display
subsystem DMA engine to rotate the frame buffer.
A VID DMA optimization is available to optimize the memory traffic (DDR memory) when 90- and
270-degree rotation is required. This optimization consists of reconstructing the RGB16 and YUV line
pixels using the cache capability of the DISPC scaler line buffers.
The pixel formats that can take advantage of the reduction in memory traffic are:
•
YUV4:2:2
1657
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
