dss-113
Z
-1
Pin(n-2)
Pin(n-1)
Pin(n)
Pin(n+1)
Pin(n+2)
C
22
C
-1
C
0
C
1
C
00
Pout(n')
Z
-1
Z
-1
Z
-1
=
−
7
)
(
)
(
)
(
2
>>
+
Φ
=
∑
=
i
i
n
Rin
Ci
n
Rout
2
i
(
)
x
dss-E066
Public Version
Display Subsystem Use Cases and Tips
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Legend:
Rout: R component output
Ci():Vertical FIR coefficients
Rin: R component input
The line (n+1) is older than line (n).
NOTE:
If the 5-tap resizer is used for RGB16 and YUV4:2:2 picture formats, the width of the input
picture must be a multiple of 2 pixels and more than 5 pixels. This leads to the following
register configuration:
[21] VIDVERTICALTAPS == 1
[10:0] VIDORGSIZEX > 4 and even
The programmable three coefficients of the poly-phase filters are signed 8-bit values (except for the
central coefficient C
0
(), which is unsigned).
The vertical filtering unit can be configured to support five taps.
The vertical 5-tap filtering macro architecture is shown in
Figure 7-148. Vertical Filtering Macro Architecture (Five Taps)
For the 5-tap vertical up/downsampling the equation is (with the example of R component):
(15)
Legend:
Rout: R component output
Ci():Vertical FIR coefficients with C
+2
()=C
00
() and C
-2
()=C
22
()
Rin: R component input
The line (n+1) is older than line (n).
1778
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
