Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Functional Description
Table 7-26. Functional Clock Frequency Requirement in RGB16 & YUV4:2:2—Active Matrix Display
Horizontal Resampling
Minimum Functional Clock
(MHz)
Off Up 1:1 – 1:2 1:2 – 1:3 1:3 – 1:4
Vertical Off AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK
Resamplin
Up AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK
g
3-tap 1:1 to 1:2 2xPCLK 2xPCLK 4xPCLK 6xPCLK 8xPCLK
5-tap 1:1 to 1:4 RatioxPCLK RatioxPCLK RatioxPCLK RatioxPCLK RatioxPCLK
With A = 1 in case all the data and synchronization signals are asserted and deasserted on the rising
edge of the PCLK; otherwise, A = 2.
Table 7-27. Functional Clock Frequency Requirement in RGB24—Active Matrix Display
Horizontal Resampling
Minimum Functional Clock
(MHz)
Off Up 1:1 – 1:2 1:2 – 1:3 1:3 – 1:4
Vertical Off AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK
Resamplin
Up AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK
g
3-tap 1:1 to 1:2 2xPCLK 2xPCLK 4xPCLK 6xPCLK 8xPCLK
5-tap 1:1 to 1:4 RatioxPCLK RatioxPCLK 2xRatioxPCLK 2xRatioxPCLK 2xRatioxPCLK
With A = 1 in case all the data and synchronization signals are asserted and deasserted on the rising
edge of the PCLK; otherwise, A = 2.
Use case example:
An input picture of 1024*768 is scaled to an output picture of size of 800*600 and displayed onto a LCD of
resolution1280*768 at a PCLK of 74.25 MHz with a DSS functional clock of 133 MHz.
In this example, a H+V down-sampling is done on the input picture. Firstly the Ratio V and H are
determined and the resulting maximum value is taken to calculate the functional clock frequency required.
Ratio V: h_ratio = 1.6 and v_ratio = 1.28 then Ratio = 0.4
Ratio H: Ratio = 1.28
Ratio H+V: Ratio = max (1.28, 0.4) = 1.28
In this use case, the horizontal and vertical down sampling range are 1:1–1:2. The 3-tap or 5-tap
configuration can be taken into consideration. Therefore, from
Table 7-26 and Table 7-27 , If in
RGB16-YUV4:2:2:
•
3-taps → DSS functional clock = 4 * PCLK = 297 MHz
• 5-taps → DSS functional clock = Ratio * PCLK = 95.36 MHz
If in RGB24,
•
3-taps
→
DSS functional clock = 4 * PCLK = 297 MHz
• 5-taps → DSS functional clock = 2 * Ratio * PCLK = 190.72 MHz
In this use case, the pixel format supported is RGB16-YUV4:2:2 in a 5-tap configuration.
7.4.2.4 Overlay Support
CAUTION
Enabling overlay optimization (setting the DSS. DISPC_CONTROL [12]
OVERLAYOPTIMIZATION bit) if no overlay region effectively exists (the
DSS.
DISPC_VIDn_ATTRIBUTES [0] VIDENABLE bit is cleared, with n = 1, 2)
leads to unpredictable behavior. The overlay optimization feature must be
enabled only when an overlay area exists. Before enabling the overlay
optimization, the DSS.
DISPC_GFX_WINDOW_SKIP [31:0] GFXWINDOWSKIP
bit field must be first set according to the video1 and graphics windows overlap.
1647 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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