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Display Subsystem Basic Programming Model
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Table 7-50. 90-degree DMA Rotation Example Description
Parameter
Description
Additional parameters for formulas
ba
Buffer Base Address in Memory
IW
Image Width in pixels
iw = IW-1
IH
Image Height in pixels
ih = IH-1
ps
Pixel Size (in bytes)
shows how the image is stored in memory and how it is read out to achieve a 90-degree
rotated orientation. The first pixel for the 0-degree orientation is located at the buffer base address (ba). If
the image is to be shown on an LCD screen with a 90-degree rotation, the readout starts at the 90-degree
base address (1). To proceed from one pixel to the next in the same line in the rotated orientation, the
pixel increment (2) must be applied. At the end of each line of the rotated view, the row increment (3) is
the offset to advance to the beginning of the next line in the memory buffer.
Hence, by setting the three DMA parameters (base address, pixel increment, and row increment), a
90-degree rotation can be achieved, as can 180-degree and 270-degree rotation. Each of the parameters
can also be combined with an optional mirroring on the vertical axis.
Following there is a description the setup required to perform the rotation via the DSS DMA. This rotation
mechanism is used when the image data is stored in internal SRAM.
7.5.3.4.2.1 Rotation/Mirroring Registers
To set up the rotation and/or mirroring, the following registers must be programmed:
•
Graphics pipeline (GFX):
–
DSS.
–
DSS.
–
DSS.
–
DSS.
–
DSS.
–
DSS.
–
DSS.
•
Video pipelines (VID) 1 and 2:
–
DSS.
–
DSS.
–
DSS.
–
DSS.
–
DSS.
–
DSS.
–
DSS.
to DSS.
–
DSS.
•
DSS.DISPC_xxx_BAj: These registers contain the base address of the image data at which the DSS
DMA transfer of the image starts. The register values depend on the rotation chosen (see
for the formulas). When using the LCD interface, the registers DISPC_xxx_BA0 are used. The
registers DISPC_xxx_BA1 are only used for the TV output.
•
DSS.DISPC_xxx_PIXEL_INC[15:0]: This bit field contains the DMA addressing increment after each
pixel. This bit field is used to perform the DSS DMA rotation (see
for the formula).
NOTE:
When the RGB24 packet format is selected, the only valid value is 1.
•
DSS.DISPC_xxx_ROW_INC[31:0]: This bit field contains the DMA addressing increment after each
row (line) of pixels. This bit field is used to perform the DSS DMA rotation (see
for the
formula).
1720
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
