Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-208. DISPC_VIDn_PIXEL_INC
Address Offset 0x0DC+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2
Physical address 0x4805 04DC+ ((–1)* 0x90) Instance DISC
Description The register configures the number of bytes to increment between two pixels for the buffer associated with video
window #n.
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved VIDPIXELINC
Bits Field Name Description Type Reset
31:16 Reserved Write 0s for future compatibility. RW 0x0000
Read returns 0
15:0 VIDPIXELINC Number of bytes to increment at the end of the row RW 0x0001
Encoded signed value (from -2
15
- 1 to 2
15
) to specify the number of
bytes between two pixels in the video buffer.
The value 0 is invalid. The value 1 means next pixel. The value
1+n*BPP means increment of n pixels. The value 1- (n+1)*BPP
means decrement of n pixels
Table 7-209. Register Call Summary for Register DISPC_VIDn_PIXEL_INC
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Video DMA Registers : [1]
• Rotation/Mirroring Registers : [2]
• DMA Register Settings : [3] [4]
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [5]
• Display Controller VID2 Register Mapping Summary : [6]
Table 7-210. DISPC_VIDn_FIR
Address Offset 0x0E0+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2
Physical address 0x4805 04E0+((–1)* 0x90) Instance DISC
Description The register configures the resize factors for horizontal and vertical up-/down-sampling of video window #n.
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved VIDFIRVINC Reserved VIDFIRHINC
Bits Field Name Description Type Reset
31:29 Reserved Write 0s for future compatibility. Read returns 0. RW 0x0
28:16 VIDFIRVINC Vertical increment of the up-/down-sampling filter RW 0x0000
Encoded value (from 1 to 4096). The value 0 is invalid. Values
greater than 4096 are invalid.
15:13 Reserved Write 0s for future compatibility. Read returns 0. RW 0x0
12:0 VIDFIRHINC Horizontal increment of the up-/down-sampling filter RW 0x0000
Encoded value (from 1 to 4096). The value 0 is invalid. Values
greater than 4096 are invalid.
1857 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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