Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
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Table 7-192. DISPC_GFX_TABLE_BA
Address Offset 0x0B8
Physical address 0x4805 04B8 Instance DISC
Description The register configures the base address of the palette buffer or the gamma table buffer.
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GFXTABLEBA
Bits Field Name Description Type Reset
31:0 GFXTABLEBA Base address of the palette/gamma table buffer (24-bit entries in RW 0x00000000
32-bit containers, aligned on 32-bit boundary).
Table 7-193. Register Call Summary for Register DISPC_GFX_TABLE_BA
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Graphics DMA Registers : [1] [2]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [3]
Table 7-194. DISPC_VIDn_BAj
Address Offset 0x0BC + ((n–1)* 0x90) + (j* 0x04) Index n = 1 for VID1 or 2 for VID2
j = 0 to 1
Physical address 0x4805 04BC+ ((n–1)* 0x90) + (j* Instance DISC
0x04)
Description The register configures the base address of the video buffer for video window #n(#j for ping-pong mechanism with
external trigger, based on the field polarity: 0 for even field and 1 for odd field).
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VIDBA
Bits Field Name Description Type Reset
31:0 VIDBA Video base address RW 0x00000000
Base address of the video buffer (aligned on pixel size boundary)
Table 7-195. Register Call Summary for Register DISPC_VIDn_BAj
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Video DMA Registers : [1] [2]
• Rotation/Mirroring Registers : [3]
• DMA Register Settings : [4] [5]
Display Subsystem Use Cases and Tips
• Register List : [6]
Display Subsystem Register Manual
• Display Controller VID1 Register Mapping Summary : [7]
• Display Controller VID2 Register Mapping Summary : [8]
1850Display Subsystem SWPU177N – December 2009 – Revised November 2010
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