Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1866 / 3738

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Display Subsystem Register Manual
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Table 7-237. Register Call Summary for Register DISPC_CPR_COEF_G
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• LCD-Specific Control Registers : [1]
• LCD Color Phase Rotation : [2] [3]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [4]
Table 7-238. DISPC_CPR_COEF_B
Address Offset 0x228
Physical address 0x4805 0628 Instance DISC
Description This register configures the color phase rotation matrix coefficients for the blue component. Shadow register,
updated on VFP start period.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR BG BB
Reserved Reserved
Bits Field Name Description Type Reset
31:22 BR BR coefficient RW 0x000
Encoded signed value (from -512 to 511)
21 Reserved Write 0s for future compatibility. Read returns 0. RW 0
20:11 BG BG coefficient RW 0x000
Encoded signed value (from -512 to 511)
10 Reserved Write 0s for future compatibility. Read returns 0. RW 0
9:0 BB BB coefficient RW 0x000
Encoded signed value (from -512 to 511)
Table 7-239. Register Call Summary for Register DISPC_CPR_COEF_B
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• LCD-Specific Control Registers : [1]
• LCD Color Phase Rotation : [2] [3]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [4]
Table 7-240. DISPC_GFX_PRELOAD
Address Offset 0x22C
Physical address 0x4805 062C Instance DISC
Description This register configures the graphics FIFO. Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PRELOAD
Bits Field Name Description Type Reset
31:12 Reserved Write 0s for future compatibility. Read returns 0. RW 0x00000
11:0 PRELOAD Graphics preload value: Number of bytes defining the preload value. RW 0x100
Constraint: Maximum value is (FIFO size - DMA burst size - 8) bytes
1866 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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