Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1840 / 3738

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
0x1: Ac-bias is active low (active display mode)
14 IPC Invert pixel clock RW 0
0x0: Data is driven on the LCD data lines on the rising-edge of the
pixel clock
0x1: Data is driven on the LCD data lines on the falling-edge of the
pixel clock
13 IHS Invert HSYNC RW 0
0x0: Line clock pin is active high and inactive low
0x1: Line clock pin is active low and inactive high
12 IVS Invert VSYNC RW 0
0x0: Frame clock pin is active high and inactive low
0x1: Frame clock pin is active low and inactive high
11:8 ACBI AC-bias pin transitions per interrupt RW 0x0
Value (from 0 to 15) used to specify the number of AC Bias pin transitions
7:0 ACB AC-bias pin frequency RW 0x00
Value (from 0 to 255) used to specify the number of line clocks to count
before transitioning the ac-bias pin. This pin is used to periodically invert
the polarity of the power supply to prevent DC charge build-up within the
display.
Table 7-165. Register Call Summary for Register DISPC_POL_FREQ
Display Subsystem Environment
• Transaction Timing Diagrams : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
[24] [25] [26] [27] [28] [29]
• Video Port (VP) Interface : [30]
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [31]
• LCD-Specific Control Registers : [32]
• LCD Timings : [33] [34] [35] [36] [37] [38] [39] [40]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [41]
Table 7-166. DISPC_DIVISOR
Address Offset 0x070
Physical address 0x4805 0470 Instance DISC
Description The register configures the divisors.
Shadow register, updated on VFP start period
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LCD Reserved PCD
Bits Field Name Description Type Reset
31:24 Reserved Write 0s for future compatibility. RW 0x00
Read returns 0
23:16 LCD Display Controller Logic Clock Divisor RW 0x01
Value (from 1 to 255) to specify the frequency of the display controller
logic clock based on the function clock. The value 0 is invalid.
15:8 Reserved Write 0s for future compatibility. RW 0x00
Read returns 0
7:0 PCD Pixel Clock Divisor RW 0x02
Value (from 1 to 255) to specify the frequency of the pixel clock based on
the Logic clock which is the functional clock divided by LCD. The values 0
and 1 are invalid.
1840 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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