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Display Subsystem Environment
NOTE:
•
The byte on Dn is sent before the byte on Dn+1, all the combinations of data and clock
are supported through programming of the DSS.
register. The
CLOCK_POSITION and CLOCK_POL bit fields configure which lane transmits the clock
and define its polarity. Four bit fields (DATA1_POSITION, DATA1_POL,
DATA2_POSITION, and DATA2_POL) configure the data lanes and their polarity. The
DATA2_POSITION bit field can be set to 0; in this case, only the data lane defined in
the DATA1_POSITION bit field is used, and data is transmitted on only one clock lane
and one data lane.
•
The configuration of the DSI complex I/O (number of data lanes, position, differential
order) must not be changed while DSS.
[20] LP_CLK_ENABLE bit is set
to 1. For the hardware to recognize a new configuration of the complex I/O (done in
DSS.
register), it is recommended to follow this sequence:
First set the DSS.
[0] IF_EN bit to 1, next reset the DSS.
[0] IF_EN
to 0, then set DSS.
[20] LP_CLK_ENABLE to 1, and finally, set again the
[0] IF_EN bit to 1. If the sequence is not followed, the DSI complex I/O
configuration is undetermined.
•
Only DATA1 is bidirectional in command mode. The low-power received information is
always sent by the display panel using DATA1. Since any lane of the DSI complex I/O
can be configured as data lane DATA1, all lanes of the complex I/O are bidirectional
7.2.2.1.2 ULPS
Each lane can be put in ultra-low power state (ULPS) by software configuration. The ULPS mode requires
all the following conditions:
•
The lane must be in stop state.
•
For data lanes, no data must be pending in the DSI module.
•
For data lane 1, no BTA should have been sent. The DSI module should have control of the bus.
The control of each lane is independently controlled by the DSS.
register.
7.2.2.2
Video Port (VP) Interface
NOTE:
The signals described in this section are internal and not bounded outside the device. This
section aims at helping software users understand the internal connections between the
display controller (DISPC) and the DSI protocol engine.
summarizes the video interface signals. This interface is used to connect the display controller
to the DSI protocol engine to send real time data streams. Note that only the active matrix timings are
supported by DSI protocol engine. The HSYNC/VSYNC/DE/DATA signals are driven on the rising or
falling edge of the pixel clock (VP_PCLK).
Table 7-10. Video Interface for DSI Protocol Engine
Signal Name
Type
(1)
Description
VP_HSYNC
I
Horizontal sync signal
VP_VSYNC
I
Vertical sync signal
VP_DATA[23:0]
I
Parallel output data: Bits 0 to 23
VP_PCLK
I
Pixel clock. In case of STALL configuration, it is used to indicate when new data
is on the data bus during the clock period of VP_CLK. The VP_PCLK is
generated from VP_CLK through division. The clock ratio is defined in the
DSS.
[4] VP_CLK_RATIO bit and must be aligned with the
configuration of the clock divisor in the display controller
(DSS.
[7:0] PCD bit field).
VP_DE
I
Data enable
(1)
I = Input, O = Output
1587
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated