Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1936 / 3738

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
18:16 VC2_FIFO_ADD Address of the space allocated in the FIFO for VC 2. For a RW 0x0
complete description, refer to Table 7-67 .
15:12 VC1_FIFO_SIZE Size of the FIFO allocated for VC 1. For a complete description, RW 0x0
refer to Table 7-66 .
11 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
10:8 VC1_FIFO_ADD Address of the space allocated in the FIFO for VC 1. For a RW 0x0
complete description, refer to Table 7-67 .
7:4 VC0_FIFO_SIZE Size of the FIFO allocated for VC 0. For a complete description, RW 0x0
refer to Table 7-66 .
3 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
2:0 VC0_FIFO_ADD Address of the space allocated in the FIFO for VC 0. For a RW 0x0
complete description, refer to Table 7-67 .
Table 7-403. Register Call Summary for Register DSI_RX_FIFO_VC_SIZE
Display Subsystem Basic Programming Model
• Command Mode RX FIFO : [0] [1] [2]
Display Subsystem Use Cases and Tips
• Configure DSI Protocol Engine : [3]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [4]
Table 7-404. DSI_COMPLEXIO_CFG2
Address Offset 0x0000 0078
Physical Address 0x4804 FC78 Instance DSI_PROTOCOL_ENGINE
Description COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane
configuration for the ULPS for each lane.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
LP_BUSY
HS_BUSY
RESERVED RESERVED RESERVED RESERVED
LANE3_ULPS_SIG2 LANE2_ULPS_SIG2 LANE1_ULPS_SIG2 LANE3_ULPS_SIG1 LANE2_ULPS_SIG1 LANE1_ULPS_SIG1
Bits Field Name Description Type Reset
31:18 RESERVED Write 0s for future compatibility. RW 0x0000
Reads returns 0.
17 LP_BUSY Indicates when there are still pending operations for VCs configured for R 0x0
LP mode. Forced to 1 when at least one VC is enabled and configured for
LP mode.
Read 0x0: LP logic is idle
Read 0x1: LP logic is active
16 HS_BUSY Indicates when there are still pending operations for VCs configured for R 0x0
HS mode. Forced to 1 when at least one VC is enabled and configured
for HS mode
Read 0x0: HS logic is idle
Read 0x1: HS logic is active
15:10 RESERVED Write 0s for future compatibility. RW 0x00
Reads returns 0.
1936 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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