Texas Instruments OMAP36 Series, Technical Reference Manual

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dss-E128
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FCLKIN4DDR FCLKIN 4
Re gN (FDSI _ PLL _ REFCLK / F INt) 1
FDSI _ PLL _ REFCLK 26 MHz (system clock)
Fint 2 MHz (reduce PLL lock time)
Re gN 12
dss-E129
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Re gM ((Re gN 1) (FCLKIN4DDR /(2 FDSI _ PLL _ REFCLK)))
FCLKIN4DDR 4 150 MHz
Re gM 150
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(4) Calculate M divider for PLL:
7.6.5.1.2.3 Switch to DSI PLL Clock Source
Table 7-104 lists the sequence to switch the DSI and DISPC module clocks to DSI PLL clock source.
Table 7-104. Switch to DSI PLL Clock Source
Steps Register/Bit Field/Programming Value
Switch DISPC clock to DSI1_PLL_FCLK. DSS_CONTROL [0] DISPC_CLK_SWITCH 0x1
Switch DSI clock to DSI2_PLL_FCLK. DSS_CONTROL [1] DSI_CLK_SWITCH 0x1
7.6.5.1.2.4 Configure DSI Protocol Engine
7.6.5.1.2.4.1 Set Up DSI Control Registers
Table 7-105 lists the steps required to set up the DSI control registers. Table 7-106 lists the steps to set
up the DSI complex I/O registers.
Table 7-105. DSI Control Registers
Steps Register/Bit Field/Programming Value
Enable SYNCLOST event. DSI_IRQENABLE [18] SYNC_LOST_IRQ_EN 0x1
Enable IRQ to indicate that packet has been
DSI_VC1_IRQENABLE[2] PACKET_SENT_IRQ 0x1
sent on VC1.
Enable IRQ to indicate that packet has been
DSI_VC0_IRQENABLE[2] PACKET_SENT_IRQ 0x1
sent on VC0.
Set the trigger reset mode to immediate. DSI_CTRL [14] TRIGGER_RESET_MODE 0x1
Activate the two line buffers. DSI_CTRL [13:12] LINE_BUFFER 0x2
Set the size of the video port data bus to 24
DSI_CTRL [7:6] VP_DATA_BUS_WIDTH 0x2
bits (RGB 888).
Define the ratio between VP_CLK and
DSI_CTRL [4] VP_CLK_RATIO 0x1
VP_PCLK.
Set the arbitration scheme for granting the VC
pending ready requests in the TX FIFO as
DSI_CTRL [3] TX_FIFO_ARBITRATION 0x1
sequential scheme.
Enable the ECC check for the received header. DSI_CTRL [2] ECC_RX_EN 0x1
Table 7-106. DSI Complex I/O Registers
Steps Register/Bit Field/Programming Value
Determine the position of the clock lane. DSI_COMPLEXIO_CFG1 [2:0] CLOCK_POSITION 0x2
Determine the position of data 1 lane. DSI_COMPLEXIO_CFG1 [6:4] DATA1_POSITION 0x3
Turn on COMPLEXIO. DSI_COMPLEXIO_CFG1 [28:27] PWR_CMD 0x1
Enable the synchronization of the shadow
DSI_COMPLEXIO_CFG1 [30] GOBIT 0x1
registers with DISPC_UPDATE_SYNC.
1806Display Subsystem SWPU177N – December 2009 – Revised November 2010
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