Public Version
Display Subsystem Environment
www.ti.com
Table 7-10. Video Interface for DSI Protocol Engine (continued)
Signal Name
Type
(1)
Description
VP_STALL
O
The stall signal must be deasserted to receive pixel and asserted to stop
receiving pixel. (It can be used only while the display controller is configured in
STALL mode; in that mode, HSYNC and VSYNC are not generated).
VP_CLK
I
Display controller internal clock. It is a free-running clock.
NOTE:
•
The polarities of VP_HSYNC and VP_VSYNC are programmable by setting the
DSS.
register.
•
The maximum frequency for VP_CLK is 173 MHz at nominal voltage, and 96 MHz at low
voltage.
•
Clocks VP_CLK and VP_PCLK can have the same frequency.
•
The number of bits to be captured on the video port is defined in the
DSS.
[7:6] VP_DATA_BUS_WIDTH bit field.
•
VP_DE is connected to the dss_acbias signal in the display controller, and its polarity
can be controlled by setting the
[15] IEO bit.
The data received on the video port can be stored into the line buffer memories or sent directly on the DSI
interface in two cases:
•
The line buffer size is too small compared to the line from the display controller.
•
There is no line buffer instantiated. If there is no line buffer, the burst mode, defined as frequency burst
mode, cannot be used. Only the transparency burst mode is supported.
NOTE:
The DSS.
[13:12] LINE_BUFFER bit field defines the number of lines to be used
for transferring data from the video port to the DSI link.
7.2.2.2.1 Video Port Used for Video Mode
If the video port is used for video mode, the VP_STALL is not used.
lists the active signals on
the video port.
Table 7-11. Video Interface in the Context of Video Mode
Signal Name
Type
(1)
Description
VP_HSYNC
I
Horizontal sync signal
VP_VSYNC
I
Vertical sync signal
VP_DATA[23:0]
I
Parallel output data: bits 0 to 23
VP_PCLK
I
Pixel clock.
VP_DE
I
Data enable
VP_CLK
I
It is a free running clock used as the display controller functional clock. The
maximum frequency is 173 MHz at nominal voltage, and 96 MHz at low voltage.
(1)
I = Input, O = Output
Three video modes are available:
•
No line buffer: The data received on the video port are directly output of the DSI port without buffering.
The ration of VP_CLK and the DSI high-speed (HS) clock period must ensure identical throughput on
the two ports (the two clocks must be generated using the same PLL; the subsystem must provide
such configuration).
•
One line buffer:
–
The data are first stored in the line buffer; once all the data for one line are received, the DSI
protocol engine sends the whole line. The software must adjust timings to allow for the storage of
all line data into the line buffer before sending to DSI outputs. The synchronization packets are
never stored into the line buffer.
•
Two line buffers:
1588
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
