Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1581 / 3738

PIXELS
PIXELS
HSW
HFP
VFP
VSW
HBP
HSW
VBP
DISPC_PCLK
DISPC_VSYNC
DISPC_HSYNC
DISPC_ACBIAS
DISPC_DATA_LCD[23:0]
dss-017
PIXELS
HBP HSW HSW HSW
VFP
DISPC_PCLK
DISPC_VSYNC
DISPC_HSYNC
DISPC_ACBIAS
DISPC_DATA_LCD[23:0]
dss-018
PIXELS
HSW
VSW
VBP
HBP
DISPC_PCLK
DISPC_VSYNC*
DISPC_HSYNC*
DISPC_ACBIAS*
DISPC_DA
* Active Low signals
TA_LCD[23:0]
dss-019
Public Version
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Display Subsystem Environment
Figure 7-19. Active Matrix Timing Diagram of Configuration 1 (Between Frames)
Figure 7-20. Active Matrix Timing Diagram of Configuration 1 (End of Frame)
• Active matrix timing configuration 2
– DSS. DISPC_POL_FREQ [17] ONOFF bit = 1
– DSS. DISPC_POL_FREQ [16] RF bit = 1
The DISPC_HSYNC and DISPC_VSYNC signals are driven on the rising edge of DISPC_PCLK.
– DSS. DISPC_POL_FREQ [15] IEO = 1
The DISPC_ACBIAS signal is active low.
– DSS. DISPC_POL_FREQ [14] IPC = 1
The pixel data is driven on the falling edge of DISPC_PCLK.
– DSS. DISPC_POL_FREQ [13] IHS = 1
The DISPC_HSYNC signal is active low.
– DSS. DISPC_POL_FREQ [12] IVS = 1
The DISPC_VSYNC signal is active low.
Figure 7-21. Active Matrix Timing Diagram of Configuration 2 (Start of Frame)
1581 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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