Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1582 / 3738

Pixels Pixels
HBP HFP
HSW HSW
HBP
DISPC_PCLK
DISPC_VSYNC*
DISPC_HSYNC*
DISPC_ACBIAS*
DISPC_DA
*Active-low signals
TA_LCD[23:0]
dss-020
PIXELS PIXELS
HSW
HFP
VFP VSW
HBP
HSW
VBP
DISPC_PCLK
DISPC_VSYNC*
DISPC_HSYNC*
DISPC_ACBIAS*
DISPC_DA
*Active Low signals
TA_LCD[23:0]
dss-021
PIXELS
HBP
HSW HSW HSW
VFP
DISPC_PCLK
DISPC_VSYNC*
DISPC_HSYNC*
DISPC_ACBIAS*
DISPC_DA
* Active Low signals
TA_LCD[23:0]
dss-022
Public Version
Display Subsystem Environment
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Figure 7-22. Active Matrix Timing Diagram of Configuration 2 (Between Lines)
Figure 7-23. Active Matrix Timing Diagram of Configuration 2 (Between Frames)
Figure 7-24. Active Matrix Timing Diagram of Configuration 2 (End of Frame)
• Active matrix timing configuration 3
– DSS. DISPC_POL_FREQ [17] ONOFF bit = 1
– DSS. DISPC_POL_FREQ [16] RF bit = 1
The DISPC_HSYNC and DISPC_VSYNC signals are driven on the rising edge of DISPC_PCLK.
– DSS. DISPC_POL_FREQ [15] IEO = 0
The DISPC_ACBIAS signal is active high.
– DSS. DISPC_POL_FREQ [14] IPC = 0
The pixel data are driven on the rising edge of DISPC_PCLK.
– DSS. DISPC_POL_FREQ [13] IHS = 0
The DISPC_HSYNC signal is active high.
– DSS. DISPC_POL_FREQ [12] IVS = 0
The DISPC_VSYNC signal is active high.
1582 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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