Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1577 / 3738

LCD
controller
output pins
Pixel clock
(Pix1)
B1
(Pix1)
B7
(Pix1)
B0
(Pix2)
B0
(Pix3)
B0
(Pix1)
R0
(Pix1)
R5
(Pix1)
R6
(Pix1)
R7
(Pix2)
B1
(Pix2)
R0
(Pix2)
R7
(Pix3)
B7
(Pix3)
R5
(Pix2)
B7
(Pix2)
R5
(Pix3)
R6
(Pix2)
R6
(Pix3)
B1
(Pix3)
R0
(Pix3)
R7
Pixel
data
[23:0]
Pixel data
dss-011
dss_data[0]
dss_data[1]
dss_data[7]
dss_data[16]
dss_data[21]
dss_data[22]
dss_data[23]
(Pix1)
G0
(Pix2)
G0
(Pix3)
G0
(Pix1)
G7
(Pix2)
G7
(Pix3)
G7
dss_data[8]
dss_data[15]
DISPC_FCLK
DISPC_PCLK
DISPC_DATA_STALL
DISPC_LCD_DATA[23:0]
4_DISPC_CLK_cycle_for_assertion
PIXELS 1 PIXELS 2 PIXELS 3 PIXELS 4 PIXELS 5
1_DISPC_CLK.cycle_after_for_de_assertion
dss-134
Public Version
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Display Subsystem Environment
Figure 7-11. LCD Pixel Data Color24 Active Matrix
7.2.1.1.4 Transaction Timing Diagrams
• Timing diagrams in flow control mode
– Stall signal
The stall signal is used in RFBI and DSI modes. In the case of RFBI mode, it is used to indicate
when the display controller must stop sending data over the LCD output interface. The RFBI
module asserts the stall signal to stop data output by the display controller. It is deasserted to
indicate when new data must be outputted by the display controller.
Figure 7-12. RFBI Data Stall Signal Diagram
To avoid underflow of the DMA FIFO, the FIFO handcheck feature can be enabled by setting the
DSS.
DISPC_CONFIG [16] FIFOHANDCHECK bit to 1. The fullness of the FIFOs associated with
the pipelines used for the LCD output is checked when the STALL signal is inactive before
providing data to the pipeline. This prevents emptying the FIFO when the RFBI module requests
data and there is not enough data in the display controller DMA FIFO. This feature must be enabled
only when the STALL mode is used (DSS.
DISPC_CONTROL [11] STALLMODE bit set to 1).
When the FIFO handcheck feature is activated, the pixel transfer to the RFBI module during STALL
inactivity period can be stopped (no DISPC_PCLK pulse) and restarted when there is enough data
in the FIFO. The FIFO handcheck ensures that underflow cannot occur for the pipelines associated
with the LCD output in RFBI mode.
Figure 7-13 details the RFBI data stall with FIFO handcheck
mode activated.
1577 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated