Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1580 / 3738

DISPC_PCLK
DISPC_VSYNC
DISPC_HSYNC
DISPC_ACBIAS
DISPC_DATA_LCD[23:0]
PIXELS
HSW VSW
VBP HBP
dss-015
PIXELS
HBP HFP
HSW HSW
HBP
PIXELS
DISPC_PCLK
DISPC_VSYNC
DISPC_HSYNC
DISPC_ACBIAS
DISPC_DATA_LCD[23:0]
dss-016
Public Version
Display Subsystem Environment
www.ti.com
Table 7-7. Programmable Fields in Bypass Mode (continued)
Name Register Description
VFP DSS. DISPC_TIMING_V [19:8] VFP bit field value Vertical front porch
VSW DSS. DISPC_TIMING_V [7:0] VSW bit field value + 1 Vertical synchronization pulse width
ONOFF DSS. DISPC_POL_FREQ [17] ONOFF bit DISPC_HSYNC and DISPC_VSYNC pixel clock
control
RF DSS. DISPC_POL_FREQ [16] RF bit DISPC_HSYNC and DISPC_VSYNC pixel clock
edge control
IEO DSS. DISPC_POL_FREQ [15] IEO bit Invert DISPC_ACBIAS
IPC DSS. DISPC_POL_FREQ [14] IPC bit Invert DISPC_PCLK
IHS DSS. DISPC_POL_FREQ [13] IHS bit Invert DISPC_HSYNC
IVS DSS. DISPC_POL_FREQ [12] IVS bit Invert DISPC_VSYNC
• Active matrix timing configuration 1
– DSS. DISPC_POL_FREQ [17] ONOFF bit = 0
– DSS. DISPC_POL_FREQ [16] RF bit = 0
The DISPC_HSYNC and DISPC_VSYNC signals are driven on the opposite edge of DISPC_PCLK
from the pixel data.
– DSS. DISPC_POL_FREQ [15] IEO = 0
The DISPC_ACBIAS signal is active high.
– DSS. DISPC_POL_FREQ [14] IPC = 0
The pixel data are driven on the rising edge of DISPC_PCLK.
– DSS. DISPC_POL_FREQ [13] IHS = 0
The DISPC_HSYNC signal is active high.
– DSS. DISPC_POL_FREQ [12] IVS = 0
The DISPC_VSYNC signal is active high.
Figure 7-17. Active Matrix Timing Diagram of Configuration 1 (Start of Frame)
Figure 7-18. Active Matrix Timing Diagram of Configuration 1 (Between Lines)
1580 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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