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Display Subsystem Register Manual
Table 7-234. DISPC_CPR_COEF_R
Address Offset
0x220
Physical address
0x4805 0620
Instance
DISC
Description
This register configures the color phase rotation matrix coefficients for the red component. Shadow register,
updated on VFP start period.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RR
RG
RB
Reserved
Reserved
Bits
Field Name
Description
Type
Reset
31:22
RR
RR coefficient
RW
0x000
Encoded signed value (from -512 to 511)
21
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0
20:11
RG
RG coefficient
RW
0x000
Encoded signed value (from -512 to 511)
10
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0
9:0
RB
RB coefficient
RW
0x000
Encoded signed value (from -512 to 511)
Table 7-235. Register Call Summary for Register DISPC_CPR_COEF_R
Display Subsystem Basic Programming Model
•
Display Controller Basic Programming Model
:
•
LCD-Specific Control Registers
•
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
Table 7-236. DISPC_CPR_COEF_G
Address Offset
0x224
Physical address
0x4805 0624
Instance
DISC
Description
This register configures the color phase rotation matrix coefficients for the green component. Shadow register,
updated on VFP start period.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
GR
GG
GB
Reserved
Reserved
Bits
Field Name
Description
Type
Reset
31:22
GR
GR coefficient
RW
0x000
Encoded signed value (from -512 to 511)
21
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0
20:11
GG
GG coefficient
RW
0x000
Encoded signed value (from -512 to 511)
10
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0
9:0
GB
GB coefficient
RW
0x000
Encoded signed value (from -512 to 511)
1865
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated