Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Use Cases and Tips
7.6.4.4 Configure the DISPC
7.6.4.4.1 Reset DISPC
Table 7-93 lists the step sequence to reset the DISPC.
Table 7-93. Reset DISPC
Steps Registers Value
Reset the DISPC. DISPC_SYSCONFIG [1] SOFTRESET 0x1
DISPC is reset. DISPC_SYSCONFIG [0] RESETDONE Read 0x1
No standby: MStandby is never asserted. DISPC_SYSCONFIG [13:12] MIDLEMODE 0x1
Disable idle mode. DISPC_SYSCONFIG [4:3] SIDLEMODE 0x1
Disable all interrupts. DISPC_IRQENABLE [31:0] 0x0
7.6.4.4.2 Configure DISPC Timing, Window, and Color
Table 7-94 lists the steps to configure the DISPC registers. Table 7-95 lists the steps to configure the
color space coefficient registers.
Table 7-96 lists the steps to configure DISPC_CONTROL .
Table 7-94. Configure DISPC Registers
Steps Registers Value
Set horizontal timings. DISPC_TIMING_H (HBP – 1<<20)|(HFP – 1<<8)|HSA – 1
Set vertical timing. DISPC_TIMING_V (HBP – 1<<20)|(HFP – 1<<8)|HSA – 1
Set LCD – PCD display controller and pixel
DISPC_DIVISOR LDC = %1 PXLCLK = %4
clock divisor.
Set the size of the LCD – 1. DISPC_SIZE_LCD (LPP – 1 + DSI_VFP)<<16|(PPL – 1)
Set default RGB value when there is no
DISPC_DEFAULT_COLOR0 0XFF
data.
Set video FIFO height and low threshold. DISPC_VID1_FIFO_THRESHOLD 0xfc00c0
Set the X Y location of the upper left pixel (0
DISPC_VID1_POSITION 0x0
= 0) to the upper left corner.
Set size of the window. DISPC_VID1_SIZE (LPP – 1) <<16|(PPL – 1)
Set the size of the picture. DISPC_VID1_PICTURE_SIZE (LPP – 1) <<16|(PPL – 1)
Set the input address picture. DISPC_VID1_BA0 0x–
Table 7-95. Configure Color Space Coefficient Registers
Comments Registers Value
RCR and RY coefficients DISPC_VID1_CONV_COEF0 0X0199012A
GY and RCB coefficients DISPC_VID1_CONV_COEF1 0X012A0000
GCB and GCR coefficients DISPC_VID1_CONV_COEF2 0X079C0730
BCR and BY coefficients DISPC_VID1_CONV_COEF3 0X0000012A
BCB coefficient DISPC_VID1_CONV_COEF4 0X00000205
Table 7-96. Configure DISPC_CONTROL
Comments Registers Value
Enable pixel clock free-running. DISPC_CONTROL [27] PCLKFREEENABLE 0x1
I/O pad mode selection: Bypass DISPC_CONTROL [16] GPOUT1 0x1
I/O pad mode selection: Bypass DISPC_CONTROL [15] GPOUT0 0x1
Normal mode selected DISPC_CONTROL [11] STALLMODE 0x0
3 for RGB888 DISPC_CONTROL [9:8] TFTDATALINES 0x3
1801 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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