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Display Subsystem Register Manual
Table 7-241. Register Call Summary for Register DISPC_GFX_PRELOAD
Display Subsystem Basic Programming Model
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Display Controller Basic Programming Model
:
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Display Subsystem Register Manual
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Display Controller Register Mapping Summary
:
Table 7-242. DISPC_VIDn_PRELOAD
Address Offset
0x230+ ((–1)* 0x04)
Index
n = 1 for VID1 or 2 for VID2
Physical address
0x4805 0630+ ((–1)* 0x04)
Instance
DISC
Description
This register configures the video FIFO. Shadow register, updated on VFP start period or EVSYNC.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
PRELOAD
Bits
Field Name
Description
Type
Reset
31:12
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0x00000
11:0
PRELOAD
Video preload value: Number of bytes defining the preload value.
RW
0x100
Constraint: Maximum value is (FIFO size - DMA burst size - 8) bytes
Table 7-243. Register Call Summary for Register DISPC_VIDn_PRELOAD
Display Subsystem Basic Programming Model
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Display Controller Basic Programming Model
:
•
Display Subsystem Register Manual
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Display Controller VID1 Register Mapping Summary
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Display Controller VID2 Register Mapping Summary
7.7.2.3
RFBI Registers
Table 7-244. RFBI_REVISION
Address Offset
0x00
Physical address
0x4805 0800
Instance
RFBI
Description
This register contains the IP revision code.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
REV
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0.
R
0x000000
7:0
REV
IP revision
R
TI internal data
[7:4] Major revision
[3:0] Minor revision
Table 7-245. Register Call Summary for Register RFBI_REVISION
Display Subsystem Register Manual
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1867
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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