Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Bits Field Name Description Type Reset
1 SOURCE Selection of the source between L4 interconnect slave RW 0x0
port and video port. This bit is ignored by hardware when
video mode is selected.
0x0: All the data are provided by the L4 interconnect
slave port. Any transfer on the video port is ignored for
this VC.
0x1: If MODE=VIDEO_MODE. any data received on the
video port (pixels and enabled synchronization events
using
DSI_CTRL [17] VP_HSYNC_START,
DSI_CTRL [18] VP_HSYNC_END, DSI_CTRL [15]
VP_VSYNC_START, DSI_CTRL [16] VP_VSYNC_END,)
are sent on the VC (only one VC can be associated with
the video port, the software must ensure that no more
than one VC is enabled with the video port as the main
source for data). If MODE=COMMAND_MODE, the
VP_STALL signal is used by the protocol engine to
indicate when new data are required. The
synchronization signals are not generated by the display
controller. Regardless of the MODE, no data can be
provided on the L4 interconnect slave port.
0 VC_EN Enables the VC. RW 0x0
0x0: Disabled. The VC must be disabled for any register
change in the DSI_VCn_XXX registers the corresponding
VC ID.
0x1: Enabled. No change is allowed to the VC registers
(except for setting the bit fields/registers:
DSI_VCn_CTRL [6] BTA_EN, DSI_VCn_TE [15:0]
TE_SIZE, DSI_VCn_TE [31] TE_START,
DSI_VCn_LONG_XXX, DSI_VCn_SHORT_XXX,
DSI_VCn_IRQXXX registers).
Table 7-421. Register Call Summary for Register DSI_VCn_CTRL
Display Subsystem Environment
• Blanking : [0] [1] [2] [3]
Display Subsystem Functional Description
• Command Mode : [4] [5] [6]
• DSI-PLL Power FSM : [7] [8]
• TurnRequest FSM : [9]
• LP RX Timer : [10]
• Bus Turnaround : [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
• Tearing Effect : [28] [29] [30]
• ECC Generation : [31]
• Checksum Generation for Long Packet Payloads : [32]
Display Subsystem Basic Programming Model
• Global Register Controls : [33]
• Virtual Channels : [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44]
• Packets : [45] [46]
• Video Mode : [47] [48] [49] [50] [51] [52] [53]
• Command Mode TX FIFO : [54] [55] [56] [57] [58]
• Command Mode RX FIFO : [59]
• Command Mode DMA Requests : [60] [61] [62] [63] [64] [65]
• DSI Programming Sequence Example : [66] [67]
• Video Mode Transfer : [68] [69]
• Command Mode Transfer Example 1 : [70] [71] [72] [73] [74]
• Command Mode Transfer Example 2 : [75] [76] [77] [78] [79]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [80]
• DSI Protocol Engine Registers : [81] [82]
1945 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated