Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Functional Description
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Table 7-33. Extra NULL Packet Header (continued)
Virtual Payload size Header Header (2nd Byte): WC Header (3rd Byte): WC Header (ECC)
Channel ID ( DSI_CLK_CTRL [17:16] (1st Byte) LSB MSB
LP_CLK_NULL_PACKE
T_SIZE)
0 0x0 0x06
0x3 1 0xC9 0x1 0x1C
2 0x2 0x20
3 0x3 0x3A
Table 7-34. Extra NULL Packet Payload
Payload size Payload (1st Payload (2nd Payload (3rd byte) Payload (CRC) Payload (CRC)
( DSI_CLK_CTRL [17:16] byte) byte) LSB MSB
LP_CLK_NULL_PACKET_
SIZE)
0 NA NA NA 0xFF 0xFF
1 0 NA NA 0x87 0x0F
2 0 0 NA 0xB8 0xF0
3 0 0 0 0x33 0x39
NOTE:
• In Table 7-33 and Table 7-34 , both ECC and checksum are enabled.
• NA means not available.
7.4.3.3 DSI Transfer Modes
There are two transfer modes supported by the DSI module:
•
Video mode (VM): Pixels are received from the video port, there are some real time constraints (pixels
must be sent at the pixel frequency required by the display module) for sending the data to the display;
• Command mode (CM): Pixels can be received from the video port or from the L4 interconnect, there
are no real time constraints except that TE must be avoided by starting the transfer at the right time
during scan of the display and should be fast enough.
7.4.3.3.1 Video Mode
The video mode refers to the MIPI DPI 1.0 standard. The sync events and pixels must be sent according
to the display mode timings. Data are received from the video port. The display controller is in charge of
fetching the data from the system memory and providing the data to the DSI protocol engine using the
video port. The short packets used for the sync event are using precalculated 32-bit values. The long
packets are constructed using the header defined in DSS.
DSI_VCn_LONG_PACKET_HEADER registers.
7.4.3.3.2 Command Mode
The command mode refers to the MIPI DCS standard. The commands, parameters and pixels are sent to
the display module with limited real time constraints (as defined in
Section 7.4.3.3.1 ). The pixels can be
provided on the video port by the display controller or on the L4 interconnect port.
NOTE: In DSI command mode, the display controller must be configured in stall mode by setting
the DSS. DISPC_CONTROL [11] STALLMODE bit to 1.
The DSS. DSI_VCn_LONG_PACKET_HEADER registers are used for the header of long packets, the
DSS. DSI_VCn_SHORT_PACKET_HEADER registers are used for the short packets.
The error correction code (ECC) can be provided while writing the ECC value directly into the
DSS.
DSI_VCn_LONG_PACKET_HEADER and DSS. DSI_VCn_SHORT_PACKET_HEADER registers.
The DSS. DSI_VCn_CTRL [8] ECC_TX_EN bit indicates if the ECC value should be calculated or if the
1664 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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