MSB
Polynomial: x^16+x^12+x^5+x^0
x^0
x^5
C15 C14 C13 C12 C11
x^12
x^15
LSB
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
dss-178
Public Version
Display Subsystem Functional Description
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before packet data enters. Packet data not including the packet header then enters as a bitwise data
stream from the left, LS bit first. Each bit is fed through the CRC shift register before it is passed to the
output for transmission to the peripheral. After all bytes in the packet payload have passed through the
CRC shift register, the shift register contains the checksum. C15 contains the checksums MSB and C0 the
LSB of the 16-bit checksum. The checksum is then appended to the data stream and sent to the receiver.
Figure 7-102. 16 Bit CRC Generation Using a Shift Register
The check-sum generation/check can be enabled and disabled by software. It is defined by a common bit
for all the VCs:
•
The DSS.
[1] CS_RX_EN bit enables/disables the check-sum generation in the receive
direction.
•
The DSS.
[7] CS_TX_EN bit enables/disables the check-sum generation in the transmit
direction
7.4.3.12 End of Transfer Packet
To allow the DSI protocol (rather than the DSI_PHY) at the display to detect the HS End Of Transfer
(EOT), an EOT packet type is added. It is a fixed short packet (4 bytes) that is added at every HS-to-LP
transition. This function is enabled by the
[19] EOT_ENABLE bit.
The EOT packet has a fixed format:
•
Data Type = DI [5:0] = 0b001000
•
Virtual Channel = DI [7:6] = 0b00
•
Payload Data [15:0] = 0x0F0F
•
ECC [7:0] = 0x01
When more than one data lane is used, the bytes in the EOT packet are distributed across multiple lanes.
EOT packet generation is supported only for the end of HS transmissions. No EOT packet is added at the
end of LP transmissions. For LP reception, any EOT packet received is simply passed through the same
as any other packet, but no internal decode or use is made of the EOT information.
7.4.4 DSI PLL Controller Functionalities
7.4.4.1
DSI PLL Controller Overview
The DSI PLL controller module forms part of the display sub-system. Nevertheless, it uses the SCP (Serial
Configuration Port) and PMP (Power Management Port) ports as the primary interfaces to the DSI
protocol engine. The SCP interface is used to set the configuration of the DPLL and HSDIVIDER modules,
primarily the various counter values. The PMP port is used to control the power state of the DPLL and
HSDIVIDER modules.
provides an overview of the DSI PLL controller module inside the
display subsystem.
The DSI PLL is also used to generate the 74.25-MHz frequency used for HDTV applications.
1684
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
