Public Version
www.ti.com
Display Subsystem Environment
Table 7-15. Sync Short Packet Values
Virtual
Sync Code
Header
Header (2nd Byte):
Header (3rd Byte):
Header (ECC)
Channel ID
(1st Byte)
Data Field LSB
Data Field MSB
0x1
0x1
See note following this
table
0x0
0x11
0x11
0x21
0x21
0x31
0x31
0x1
0x41
0x1
0x11
0x51
0x21
0x61
0x31
0x91
0x0
0x0
0x1
0x81
0x2
0x11
0x81
0x21
0xA1
0x31
0xB1
0x1
0xC1
0x3
0x11
0xD1
0x21
0xC1
0x31
0xF1
NOTE:
•
If the ECC is enabled by setting the DSS.
[8] ECC_TX_EN bit to 1 for
the VC in video mode, the ECC value is calculated; otherwise, 0x00 is used for the
blanking long packets and sync short packets. If the CRC is enabled by setting the
DSS.
[7] CS_TX_EN bit to 1 for the VC in video mode, the check-sum
value is calculated; otherwise, 0x00 is used for the blanking long packets.
•
In other cases, when the DSS.
[7] CS_TX_EN bit is set to 0, the value
0x00 is always used for the CRC (long packets). When the DSS.
ECC_TX_EN bit is set to 0, the value 0x00 is used for the ECC for short and long
packets, except when the header is provided by the register, since the ECC field is
available in the register. It can be used to generate invalid ECC values when the header
is provided by the register.
The link [lane(s) and clock separately] can be put in ULPS mode. While using the blanking values formerly
defined, the packets (short and long) are considered in HS mode.
Timing parameters VSA, VBP, VFP, HSA, HBP, HFP, VACT, and t
L
are defined in the
DSS.DSI_VM_TIMINGx (x between 1 and 7) register. HSA, HBP, HFP, and t
L
are defined using the byte
clock unit (TxByteClkHS) and also in low-power clock cycles (TxClkEsc). VSA, VBP, VFP, and VACT are
defined in term of number of lines. When the HS blanking packets are sent during the blanking periods,
the parameters are used to determine the blanking packet payload size (taking into account the 4-byte
header and the 2-byte check sum).
The configuration of the display controller timing generator must be used when the display controller
timings are used to generate the DSI HS video mode transfer.
Special care must be taken in the case of the last line of the frame. The LPS transition is required when
the link is in HS mode for the whole frame.
When BTA is sent for the data packets, the following blanking period cannot be used for sending any data
from the TX FIFO. When the blanking period starts with one HS packet from one VC, it can only be
followed by another HS packet from the same VC, or by trigger (BTA for example). When there is no more
HS data to send for this VC, the lane is in LPS. When the blanking period starts with one LP packet from
one VC, it can only be followed by another LP packet from the same VC, by another VC, by trigger (BTA
1601
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
