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Display Subsystem Basic Programming Model
(threshold value bigger than space left in the TX FIFO for the VC).
NOTE:
In case the video mode is active, the blanking period should be large enough to allow the
transfer of the packet(s).
Sequential arbitration must be set (TX_FIFO_ARBITRATION[3]
bit = 0x1) if only
one VC is used to send multiple packets during the same blanking period.
When consecutive packets should be sent in HS mode, to ensure that there is no LP transition between
them at least one of the following condition should be valid:
•
Packets from the same VC
•
Short packets or long packets with a payload size multiple of 4 bytes
To flush the FIFO (discard of the data) for some pending bytes, the software should change the allocated
size of the chuck FIFO by:
•
First disabling the VC resetting DSS.
[0] VC_EN bit to 0
•
Second change the size of the space of FIFO to 0 by writing the DSS.
VCn_FIFO_SIZE (n is the VC value between 0 and 3)
If there is an on-going packet transfer from the TX FIFO to DSI_PHY, the flush of the FIFO should stop
immediately the transfer. Because the FIFO is accessible to users, it must ensure that there are no bytes
left in the FIFO before starting the flush operation. But it can be required in dead-lock situation to flush the
FIFO even if there are still bytes in the FIFO, in that case, the software should also take care of having a
known state of the whole DSI protocol engine module (software reset may be required) To start of new
transfer through the TX FIFO.
Users can check that there is no pending request before changing the size of the allocated FIFO for the
VC by reading the relevant DSS.
[15] VC_BUSY bit or by using the interrupt
PACKET_SENT_IRQ: All the packets have been sent by counting the transferred requests to the L4
interconnect port and the number of requests sent to the DSI complex I/O. This interrupt can be
monitoring by reading the DSS.
[2] PACKET_SENT_IRQ status bit.
The DSS.
[3] TX_FIFO_ARBITRATION bit defines if the arbitration scheme is:
•
Round-robin between enabled VCs with pending ready requests (pending ready request means that all
bytes for the packets are in the FIFO or the space of the FIFO for the VC is full) starting from the VC
which has the least VC ID number.
•
Sequential: All the pending ready requests for one VC are sent before moving to another VC. The
condition of "space of the FIFO is full" should be evaluated after the end of each packet.
If users want to use sequential arbitration for all requests for all channels, a single VC should be used.
(the VC ID defined in the header provided to the hardware using either the
DSS.
or DSS.
register is not
used and not modified by the DSI protocol engine).
The register DSS.
defines the allocated number of 33-bit values for each VC in
the TX FIFO and the start address for each VC. The size of the space allocated in the TX FIFO defined by
DSS.
VCn_FIFO_SIZE (n corresponds to the VC number n) bit fields should be a
multiple of the threshold defined in DSS.
[19:17] DMA_TX_THRESHOLD bit field. Only the
enabled VCs should be taken into account. To change the size of the space of the memory allocated for a
specific VC, the VC should be disabled by setting the DSS.
[0] VC_EN bit to 0. The whole
FIFO may not be used by all the VCs at a given time since a VC can be disabled to change one or
multiple parameters. Software users are responsible for correctly configuring the start address and the
size for each VC.
indicates the corresponding values for the size of the space allocated in the FIFO.
Table 7-64. Virtual Channel TX FIFO Size Values
.VCn_FIFO_SIZE[n = 0, 3]
Space Size (up to the size of the FIFO)
0
0 x 33 bits
1
32 x 33 bits
1743
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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