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Display Subsystem Register Manual
Table 7-429. Register Call Summary for Register DSI_VCn_SHORT_PACKET_HEADER
Display Subsystem Environment
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Virtual Channel ID - VC Field, DI[7:6]
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Display Subsystem Functional Description
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Display Subsystem Basic Programming Model
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Command Mode Transfer Example 1
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Display Subsystem Register Manual
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Display Subsystem Register Manual
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DSI Protocol Engine Register Mapping Summary
Table 7-430. DSI_VCn_IRQSTATUS
Address Offset
0x0000 0118+ (n* 0x20)
Index
n = 0 to 3
Physical Address
0x4804 FD18+ (n* 0x20)
Instance
DSI_PROTOCOL_ENGINE
Description
INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the
VC.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CS_IRQ
BTA_IRQ
FIFO_TX_UDF_IRQ
FIFO_TX_OVF_IRQ
FIFO_RX_OVF_IRQ
PACKET_SENT_IRQ
ECC_CORRECTION_IRQ
PP_BUSY_CHANGE_IRQ
ECC_NO_CORRECTION_IRQ
Bits
Field Name
Description
Type
Reset
31:9
RESERVED
Write 0s for future compatibility.
RW
0x000000
Reads returns 0.
8
PP_BUSY_CHANGE_IRQ
Video port ping-pong buffer busy status.
RW
0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
7
FIFO_TX_UDF_IRQ
FIFO underflow status. The FIFO used on the slave port
RW
0x0
for buffering the data received on the OCP slave port for
the VC has underflowed which means that the data for
the current packet have not been received in time since
the transfer of the packet are already started (transfer
started since the packet size is bigger than space
allocated in the FIFO).
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
1949
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated