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Display Subsystem Basic Programming Model
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engine has not been able to resynchronize the video port timing to its own timing base or if it has been
done. The RESYNCHRONIZATION_IRQ indicates software users that the video port works but the
configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to
be modified to avoid the resynchronization to occur. The SYNC_LOST_IRQ and
RESYNCHRONIZATION_IRQ events can be respectively monitored in DSS.
SYNC_LOST_IRQ and DSS.
[5] RESYNCHRONIZATION_IRQ status bits.
The DSS.
[27:24] WINDOW_SYNC bit field defines the synchronization period. The
recommended value is 0x4 based on the implementation of the resynchronization scheme.
7.5.4.9
Video Port Data Bus
The DSS.
[7:6] VP_DATA_BUS_WIDTH bit field is used to determine the width of the data bus
on the video port. The supported formats are 16-bit, 18-bit and 24-bits.
7.5.4.10 Command Mode
7.5.4.10.1 Command Mode TX FIFO
The single TX FIFO is used on the L4 interconnect port to receive the data to be sent to the peripheral.
The configuration of the FIFO for a specific VC should be done only when the VC is disabled.
Users should not enable the VC if there is still some pending data in the TX FIFO for the corresponding
space allocated for the VC from previous active period. When the VC space in the TX FIFO is empty, the
VC can be enabled.
For each VC, two dedicated DSS.
and
registers are used to provide data for long packets. The
register DSS.
is used to provide data for short packets (32-bit
long).
For each long packet, the DSS.
register should be written first and
then the DSS.
register. The only exception is when the word count
defined in the header is equal to 0. In that case, it is not required to write into the payload register. For
consecutive long packets, the header should be written into the
DSS.
register even if the value remains the same.
The TX FIFO stores all the pending bytes to be sent to the peripheral(s). Multiple receivers can be
addressed using the VC capability.
The 32-bit write requests only for each VC to the TX FIFO should be kept in order while sending the data
to the DSI_PHY inside the VC requests. The only exception is in the case of last 32-bit write for the last
bytes of the payload data since it could be 1, 2, 3, or 4 bytes.
Also in case the last transfer is a 32-bit write but the number of valid bytes is 1, 2, or 3 only (calculated
using the header word count and the number of bytes are received for the payload), the hardware should
store the 32-bit value into the TX FIFO but the invalid bytes are not sent, and are discarded.
When the word count defined in DSS.
register is not a multiple of
the request threshold value defined in DSS.
[19:17] DMA_TX_THRESHOLD bit field,
32-bit requests and/or bytes should be discarded by the hardware to store in FIFO only the exact number
of valid bytes.
The DSI protocol module should be able to determine if the bytes in the TX FIFO correspond to a short or
long packet without decoder the DT field. When the bytes are written into the
DSS.
, and
registers, the hardware should store the information
concerning long or short packet. A 1-bit flag should be used for each entry of the TX FIFO.
When the VC is disabled, the remaining bytes in the FIFO should be sent to the DSI link. The start event
to send data to the DSI link one of the following events:
•
All bytes have been received in the FIFO ( payload).
•
The space of the FIFO allocated for the VC is full.
•
The space of the FIFO allocated for the VC is not enough to request more data using DMA request
1742
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
