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ADwin-light-16

Manual

ADwin-light-16

, manual version 2.2, December 2004

Summary of Contents for ADwin-light-16

Page 1: ...ADwin light 16 Manual ADwin light 16 manual version 2 2 December 2004 ...

Page 2: ... December 2004 Jäger Computergesteuerte Messtechnik GmbH Rheinstraße 2 4 D 64653 Lorsch Germany For any questions please don t hesitate to contact us Hotline 49 6251 96320 Fax 49 6251 5 68 19 E Mail info ADwin de Internet www ADwin de ...

Page 3: ...g Inputs and Outputs 11 5 2 Digital Inputs and Outputs 13 5 3 Impulse Event Counter 13 5 4 Time critical tasks 16 6 Calibration 19 7 CO1 Counter Add On 22 7 1 Hardware 22 7 2 Programming 23 8 DIO1 Add On 24 8 1 Digital Inputs and Outputs 27 8 2 Counters 28 8 3 CAN Bus 35 9 ADwin light 16 Boot 39 10 Accessories 40 11 Software 41 11 1 Example Program 41 Annex A 1 A 1 Technical Data A 1 A 2 Hardware ...

Page 4: ...rs to further information in this documentation or to other sources such as manuals data sheets literature etc C ADwin File names and paths are placed in parentheses and characterized in the font Courier New Program text Program instructions and user inputs are characterized by the font Courier New Var_1 Source code elements such as INSTRUCTIONS variables comment and other text are characterized b...

Page 5: ...y by appropriately qualified personnel Qualified personnel are persons who due to their education experience and training as well as their knowledge of applicable technical stan dards guidelines accident prevention regulations and operating condi tions have been authorized by a quality assurance representative at the site to perform the necessary acivities while recognizing and avoiding any possib...

Page 6: ...he processor of the ADwin system executes all tasks which require real time in parallel Real time operating system The operating system for the DSP of the ADwin system has been optimized to reach the fastest response times possible It manages parallel processes in a multitasking manner Low priority processes are managed by time slicing Requested high priority processes interrupt all low priority p...

Page 7: ...means immediate and full range responds The ADwin system never sends data to the PC without request The data transfer to the PC is always a response to an instruction coming from the PC Thus embedding the ADwin system into various programming languages and standard software packages for measurements is easily made because they have only to be able to call functions and process the return value Sof...

Page 8: ...bit resolution and an output voltage range of 10 V 10 V You can synchronize and calibrate the output of the voltage of all DACs per software In order to smooth the output signal it passes through a low pass filter with a cut off frequency of fc 700 kHz Digital inputs and outputs 6 digital inputs and 6 digital outputs are available on the 37 pin D SUB socket The inputs and outputs are TTL compatibl...

Page 9: ...16 basic version are described in the following table Please take into account that the power supply for the different designs varies 5 Volt for L16 PCI L16 EURO and L16 cPCI 10 18 Volt for L16 EXT PC plug in board L16 PCI 19 plug in board L16 EURO external enclosure L16 EXT Compact PCI plug in board L16 cPCI Type Interface USB Ethernet PC plug in board L16 PCI 19 plug in module Euro L16 EURO L16 ...

Page 10: ...ur edge evaluation for the connection of incremental encoders L16 Boot Flash EPROM bootloader for standalone operation with out PC Can only be ordered in combination with an Ethernet interface L16 Mount Kit for installation of the system on a DIN rail in a control cabinet Please take into account that the counters of the add on boards are not addi tionally available but they replace the counters o...

Page 11: ...fluence on the measured signal If you want to prevent transient currents please make sure that the shielding is fully operative Take measures for bleeding off interferences such as earth ing the shielding close to the entry into the control cabinet The more frequently you earth the shielding on its way to the machine the better the shielding will operate Use cables with shielding on both ends for ...

Page 12: ...tandard scope of delivery otherwise also the external power supply if operated in a car the battery voltage If using current limiting power supplies please pay attention the current demand on power up which can be a multiple of the idle current You find more detailed information in the Technical Data Annex In case of power failure all unsaved data are lost Not defined data values can under unfavor...

Page 13: ...ut socket and a manual on off switch All inputs and outputs may only be operated according to the specifications given see Annex A 1 Technical Data In case of doubt ask the manufacturer of the device to which you want to connect the ADwin light 16 system Open inputs can cause errors above all in an environment which is not free of any interferences For your own safety set unused inputs as close as...

Page 14: ...max 100mA 12V max 100mA DGND DIGIN 5 CNTR 2 CLK DIGIN 4 CNTR 1 CLK DIGIN 3 DIGIN 2 DIGIN 1 DIGIN 0 ADC 11 INPUT ADC 09 INPUT ADC 07 INPUT ADC 05 INPUT ADC 03 INPUT ADC 01 INPUT ADC 15 INPUT ADC 13 INPUT DAC 2 OUTPUT DAC 1 OUTPUT RESERVED 12V max 100mA EVENT INPUT DIGOUT 5 DIGOUT 4 DIGOUT 3 DIGOUT 2 DIGOUT 1 DIGOUT 0 ADC 11 INPUT ADC 09 INPUT ADC 07 INPUT ADC 05 INPUT ADC 03 INPUT ADC 01 INPUT ADC ...

Page 15: ...l at the multiplexer output is converted by a 16 bit analog to digital converter ADC see Fig 2 Functions diagram with USB interface The conversion time is 10 µs at a resolution of 305 µV Complete measurement The instruction ADC executes a complete measurement with an ADC on one analog input Thus this instruction considers for instance the settling time of the multiplexer and assures perfect measur...

Page 16: ...ge differ ence and is equivalent to the voltage of the least significant bit LSB The ULSB is equivalent to the formula 20 V 216 305 175 µV The measured 16 bit value of the ADC is returned to the lower word of the binary cell Here you must also find the DAC value to be output Conversion Digits Voltage DAC For a DAC ADC For an ADC 10 10 0 32768 65536 0 V Digit Bit 31 16 15 14 13 12 11 10 09 08 07 06...

Page 17: ...ible when using a DIO1 add on and can optionally be used for both purposes The digital inputs and outputs are TTL compatible and not protected against overvoltage Do not use connections marked as RESERVED They are reserved for upcoming changes or expansions and can cause damages to your system if you do not pay attention to this fact Trigger input EVENT The ADwin light 16 system is equipped with a...

Page 18: ...pull down resistor Neverthe less open ended inputs can cause errors in an environment which is not free of interferences Therefore set the unused inputs to a defined level e g GND 5 3 2 Software Include file The counters are easily programmed by using ADbasic instructions The instructions are part of an include file which must be included at the beginning of a program INCLUDE ADWL16 INC The instru...

Page 19: ... type INTEGER or LONG The representation of 32 bit values in ADbasic often leads to confusion because the signless counter value is shown as signed decimal number see circle below Consequently a transition between positive and negative range of numbers is shown on the screen which yet is of no importance to the eval uation of the counter contents For completion the following describes the interpre...

Page 20: ...ramming closely to the hardware Analog inputs and outputs ADC Execute the following ADbasic instructions instead of the standard instruction ADC according to the following order Program structure SET_MUX wait for settling time START_CONV WAIT_EOC wait for end of conversion READADC It is important to set a sufficient time delay using additional programming instructions between the instructions STAR...

Page 21: ...0 end conversion e 1 conversion is running 20 40 00 30 read register ADC 1 x x x x x x x x x x x x result of the conversion 20 40 01 00 read register and start conversion ADC 1 x x x x x x x x x x x Fig 13 ADC hardware addresses of the control and data registers Address Function Bit no Comment HEX 31 16 15 10 9 8 7 6 5 4 3 2 1 0 20 40 00 10 start conversion all DAC synchro nously 1 1 s 1 1 s 0 sta...

Page 22: ...x x x x x x x x x latched counter value 20 40 03 00 enable disable counter CNT_ENABLE 0 0 counter disabled 1 1 counter enabled 20 40 03 10 clear counter CNT_CLEAR 0 0 no effect 1 1 clear counter 20 40 03 20 latch counter CNT_LATCH 0 0 no effect 1 1 latch counter value into latch A The bits are reset after the function has been executed All other functions are reset by the opposing function Fig 16 ...

Page 23: ...ly you connect DAC 1 to ADC 01 DAC 2 to ADC 03 and AGND DAC with ADC 01 and ADC 03 for instance in form of a test connector You need these connections also for the calibration diagram connection cables from the inputs outputs to the reference voltage source and to the measurement device Step 1 Connect your ADwin light 16 system with the PC and configure it with the pro gram ADconfig exe Step 2 Sta...

Page 24: ... is effected in 3 steps you can switch between the windows of the steps by using the forward backward buttons Calibration is also possible without reference voltage source but it will not be so precise Calibrate first the DAC1 and DAC2 and then the ADC Step 3 The 3 levels for calibrating a converter are described below for the DAC in the left column and for the ADC in the right column 1 Connect th...

Page 25: ...ed for DAC 1 ADC 01 and graph 2 green for DAC 2 ADC 03 The deviation should be smaller than 5 digits You can print the graph with Print Graph a color printer is recommended To do so enter the serial number of your ADwin system so that you can allo cate the printout later On the printout you will also find the calibration settings and the date of print With Close you return to the overview window S...

Page 26: ...al input see also chapter 5 2 Although all inputs of the CO1 add on have a pull down resistor open ended inputs can cause errors in an environment which is not free of interferences Therefore set unused inputs on a defined level e g GND Control Register 32 bit Counter 1 32 bit Latch 1 CLK EN CLR ADwin light 16 bus Data Data A DIR B 4k7 4k7 DIR L16 PCI and L16 cPCI L16 EURO and L16 EXT Fig 18 Pin a...

Page 27: ...nding hardware addresses are illustrated The hardware addresses of the CO1 counters are identical with or replace those of the basic counter version Counter no 1 Comment Bit 0 CNT_CLEAR 0 no effect 1 clear counter CNT_ENABLE 0 disable counter 1 enable counter pay attention to running counters CNT_LATCH 0 no effect 1 copy counter value into latch A CNT_READLATCH read latch A counter no 1 CNT_READ c...

Page 28: ...TOR is similar to the basic version except one difference The pins 15 16 in the basic version each with double functions are now solely used as DIGIN 04 and DIGIN 05 Fig 21 Block diagram of L16 DIO1 with USB interface 8 dig I O lines TTL 5V CMOS 8 dig I O lines TTL 5V CMOS 6 digital inputs TTL 5V CMOS 6 digital outputs TTL 5V CMOS 16bit 10µs A D MUX IN 1 IN 3 IN 5 IN 7 IN 9 IN 11 IN 13 IN 15 D A S...

Page 29: ... 5 4 3 2 1 DGND 5V max 100mA EVENT INPUT DIO BIT 23 DIO BIT 22 DIO BIT 21 DIO BIT 20 DIO BIT 19 DIO BIT 18 DIO BIT 17 DIO BIT 16 DIO BIT 07 DIO BIT 06 DIO BIT 05 DIO BIT 04 DIO BIT 03 DIO BIT 02 DIO BIT 01 DIO BIT 00 DGND 5V max 100mA DIO BIT 31 DIO BIT 30 DIO BIT 29 DIO BIT 28 DIO BIT 27 DIO BIT 26 DIO BIT 25 DIO BIT 24 DIO BIT 15 DIO BIT 14 DIO BIT 13 DIO BIT 12 DIO BIT 11 DIO BIT 10 DIO BIT 09 ...

Page 30: ...s shown in the Annex Fig 23 Position of the DIP switches on the DIO1 PCB CNTR 1 CNTR 2 diff s e diff s e CAN Term off on LM3940 74HCT245 74HCT245 ADM 706 OCX 16MHz OCX 40MHz MAX 3098 MAX 3098 XILINX FPGA XCS20XL 74HCT245 74HCT245 OPA 2132 A82 C250 74ACT16245 CAN Controller AN82527 LightExp03 035 035 17S30 LPC ...

Page 31: ...inst overvolt age Power up configuration After power up all connections are configured as inputs this corresponds to the instruction CONF_DIO_E 0 With the instruction CONF_DIO_E n You program the 32 DIO lines in 4 groups with 8 lines each as input or output see online help The following table shows the 16 possible configurations you will get with this instruction In order to use this instruction y...

Page 32: ...rements the counter value by one The signal at DIR determines the counting direction 0 down 1 up Four edge evaluation Every edge of the signals off phase by 90 degrees at A CLK and B DIR causes the counter to increment decrement The counting direction is determined by the sequence of the rising falling edges of these signals This mode is particularly used for incremental encoders Internal clock 5 ...

Page 33: ...counter CNT_ENABLE The instruction CNT_ENABLE always accesses all counters Even if you want to change the status disabled enabled of only one counter you Counter no 2 1 Comment Bit 1 0 CNT_CLEAR 0 0 no effect 1 1 clear counter CNT_ENABLE 0 0 disable counter 1 1 enable counter pay attention to running counters CNT_INPUTMODE 0 0 set CLR LATCH input to CLR mode 1 1 set CLR LATCH input to LATCH mode C...

Page 34: ...er 2 x x x x x x x x x x x x x contents of the latch 20 40 02 18 contents of latch B counter 2 x x x x x x x x x x x x x contents of the latch 20 40 03 00 enable disable counter CNT_ENABLE x x x x x 0 disable counter x 1 enable counter 20 40 03 10 clear counter CNT_CLEAR x x x x x 0 no effect x 1 clear counter 20 40 03 20 latch counter CNT_LATCH x x x x x 0 no effect x 1 latch counter 20 40 03 30 ...

Page 35: ... used to Clearing clear the counter CLR Latching latch the counter value into latch A LATCH Clock and direction Every positive edge of a square wave signal at the clock input CLK is counted incremented or decremented up to a maximum frequency of 20 MHz The direction is derived from a high signal increment or low signal decrement at the direction input DIR this signal can be a fixed voltage or a dy...

Page 36: ...an 50 ns Impulse widths or pause durations shorter than 100 ns are not incre mented Changing the phase shift to 90 degrees will have an effect on the maximum input frequency because of the minimum time lap of the edges If it differs from 90 degrees the maximum input freqeuency of 5 MHz decreases for instance to 45 degrees at 2 5 MHz INIT CNT_ENABLE 0 CNT_CLEAR 1 CNT_MODE 0 CNT_INPUTMODE 0 CNT_ENAB...

Page 37: ... in order to acquire each cycle Period duration measurement In this mode a counter value is latched into latch A at every positive edge and the previous data are overwritten The pulse width will be derived from the counter value difference multiplied by the period duration of the reference clock initialize disable counter clear counter external clock input at CLK input enable mode four edge evalua...

Page 38: ... of the latches initialize disable counter clear counter mode internal reference clock at internal CLK input of the counter with 20 MHz or with 5 MHz set input CLR LATCH to LATCH mode enable counter read latch A evaluation in the program INIT CNT_ENABLE 0 CNT_CLEAR 1 CNT_MODE 1 CNT_INPUTMODE 1 CNT_ENABLE 1 CNT_SET 0 CNT_SET 1 EVENT CNT_READLATCH 1 G 20 or 5 MHz Control Registers 32 bit Latch B 1 2...

Page 39: ...s to ISO 11898 You program the interface with ADbasic instructions which are directly accessing the controller s registers Message Messages sent via CAN bus are data telegrams with up to 8 bytes which are characterized by so called identifiers The CAN controller of the DIO1 add on supports identifiers with a length of 11 bit and 29 bit The communication that means the management of bus messages is...

Page 40: ... define the identifier of the object instruction EN_TRANSMIT Save the message in can_msg Send the message instruction TRANSMIT The message in the array can_msg is transferred to the message object As soon as the bus is ready the message is sent with the identifier of the message object Receiving messages Receiving a message is made as follows You configure a message object to receive and define th...

Page 41: ...ress 4Fh have to be changed Just use the instruction SET_CAN_BAUDRATE for setting a large quantity of bus frequen cies Special cases In some special cases it may be better to select configurations other than those set with the instruction mentioned above For this purpose specified registers have to be set with the instruction POKE The structure of the register is described below The following tabl...

Page 42: ... updated If there is no interrupt the register is set to 0 If another interrupt occurs during working with the first interrupt its source will be shown in the interrupt register An additional interrupt does not occur in this case Programming The DIO1 CAN interface is easily programmed by using ADbasic instructions The instructions are part of an include file which must be included at the begin nin...

Page 43: ... off and powering up anew the bootloader option is enabled again By programming the Flash EEPROMs without processes the system will only be booted after restart with the file ADwin9 btl A process will not be exe cuted With the installation of the ADwin Developer software from the ADwin CD ROM the program for the bootloader option ADethflash is automatically cop ied The version of the CD ROM should...

Page 44: ...ight 16 pow On the secondary side ADwin light 16 pow provides 12 Volt at a maximum continuous load of 2 Ampere The power supply is rated for the highest load and maximum expansions Cable connector In case you want to use an external power supply you need the cable connec tor for the correct connection to the ADwin light 16 system Please pay attention to a sufficient shielding of the USB and Ethern...

Page 45: ...eiver The program exchanges all 10 ms data REM between CAN controller and transputer INCLUDE ADWL16 INC DIM result AS INTEGER INIT INIT_CAN Initialize the CAN controller Set Baud rate to 125 kBit s SET_CAN_BAUDRATE 125000 EN_RECEIVE 2 385 0 configure message object 2 for reading with 11 bit identifier 385 EN_TRANSMIT 3 1 0 configure message object 3 for writing with 11 bit ident 1 EVENT REM read 1...

Page 46: ...M result status object AS INTEGER INIT INIT_CAN Initialize the CAN controller set Baud rate to 125 kBit s SET_CAN_BAUDRATE 125000 EN_RECEIVE 1 385 0 message object 1 is configured for reading Only messages with 11 bit identifier 385 are saved status GET_CAN_REG 1 read status EN_INTERRUPT 1 When a message arrives in message object 1 an interrupt is triggered EVENT object GET_CAN_REG 5Fh read interr...

Page 47: ... with Ethernet operating current L16 L16 CO1 Iidle bei Ub typ L16 PCI EURO cPCI 1 0 1 2 1 8 A L16 EXT 0 55 0 7 0 9 L16 DIO1 L16 PCI EURO cPCI 1 15 1 3 1 9 L16 EXT 0 55 0 7 1 0 inrush current L16 L16 CO1 Ipower on bei Ub typ L16 PCI EURO cPCI 6 4 A L16 EXT 3 3 L16 DIO1 L16 PCI EURO cPCI 7 5 L16 EXT 3 3 Operation temperature Tenvironment L16 PCI EURO cPCI 5 50 C Tchassis L16 EXT 5 55 relative humidi...

Page 48: ... I O lines line DIGIN05 00 DIGOUT05 00 6 inputs and 6 outputs TTL 5V CMOS level EVENT 1 ext trigger input positive TTL logic as inputs max input voltage TTL level 0 5 5 5 V logic input voltage VIH High VCC 5V 2 VIL Low VCC 5V 0 8 logic input current II VCC 5V 0 1 1 000 nA as outputs logic output voltage VOH High IOH 6mA 3 84 4 3 V VOL Low IOL 6mA 0 17 0 33 logic output current IO per DIO line 35 m...

Page 49: ...e 2 0 integral non linearity INL 1 3 LSB differential non linearity DNL 0 25 0 5 offset drift 2 ppm C error adjustable gain drift 20 ppm C error adjustable DAC 16 Bit number 2 output voltage Uout 10 9 999695 V settling time tsettle 2V step 3 µs FSR 20V 10 maximum current 5 mA integral non linearity INL 2 LSB differential non linearity DNL 1 offset error adjustable gain error adjustable FSR Full Sc...

Page 50: ...urements as well as a four edge evaluation for connection of incremental encoders The incremental counters of the basic version are replaced Counter inputs 3 differental inputs A CLK B DIR CLR LATCH for each counter counter pro grammable with differential or single ended inputs Counter and latch resolu tion 32 Bit count frequency fCLK input CLK 20 MHz input A B 5 Digital Inputs Outputs number DIO3...

Page 51: ...x contents of latch register x 20 40 02 10 write into register and start conver sion immediately DAC 2 x x x x x x x x digital value to be converted x x x 20 40 02 14 contents of Latch A counter 2 x x x x x x x x x contents of latch register x x 20 40 02 18 contents of Latch B counter 2 x x x x x x x x x contents of latch register x 20 40 03 00 enable disable counter CNT_ENABLE x x x 0 disable cou...

Page 52: ...ntrol and data registers 17 Fig 14 DAC hardware addresses of the control and data registers 17 Fig 15 DIO hardware addresses of the control and data registers 17 Fig 16 Counter hardware addresses of the control and data registers 18 Fig 17 Block diagram of the L16 CO1 counter add on 22 Fig 18 Pin assignment of L16 CO1 22 Fig 19 CO1 instructions short reference 23 Fig 20 CO1 hardware addresses of t...

Page 53: ...ADwin light 16 manual version 2 2 December 2004 A 7 Annex ADwin A 4 Index B Bus frequency CAN C CAN bus event 38 To calculate the bus frequency 37 CAN Bus Global mask 37 E Event CAN bus 38 ...

Page 54: ... Conversion EMC Electro Magnectic Compati bility ESD Electro Static Discharge FPGA Field Programmable Gate Array FSR Full Scale Range GND GrouND h Hex Hexadecimal number I O Input Output IC Integrated Circuit InAmp Instrumentation Amplifier INL Integral Non Linearity IRQ Interrupt ReQuest kB kilo Byte 1024 Byte kByte seekB LED Light Emitting Diode LSB Least Significant bit MB Mega Byte 1024kB MByt...

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