Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1683 / 3738

8 8 8
D63
D 0
0 0
D24 D23
P [ 5 : 0 ]
0 0
Parity Generator
8
ECC
DT [ 5 :0 ] VC WC [7 : 0 ] or DB 0 WC [ 15 :8 ] or DB 1
dss-176
16-bit checksum
16-bit packet footer (PF)
CRC LS byte CRC MS byte
dss-177
Public Version
www.ti.com
Display Subsystem Functional Description
7.4.3.10 ECC Generation
The DSI protocol uses a four-byte packet header. Since ECC generation requires a fixed word length of
64-bits, the packet headers should be padded with additional bits to form a full eight-byte value for ECC
generation and checking. The packet header less the ECC byte should occupy bits D[23:0] and the pad
bits should occupy bits D[63:24]. All padding bits should be zero for the purpose of generating the ECC
byte. ECC can be generated using a parallel approach as illustrated in
Figure 7-100 .
Figure 7-100. 64-Bit ECC Generation on TX Side
The ECC generation/check can be enabled and disabled by software. It is defined by a common bit for all
the VCs:
•
The DSS. DSI_CTRL [2] ECC_RX_EN bit enables/disables the ECC generation in the receive direction.
• The DSS. DSI_VCn_CTRL [8] ECC_TX_EN bit enables/disables the ECC generation in the transmit
direction
7.4.3.11 Checksum Generation for Long Packet Payloads
Long packets are comprised of a packet header protected by an ECC byte and a payload of 0 to 2
16
- 1
bytes. To detect the errors during the transmission of long packets, a checksum is calculated over the
payload portion of the data packet. Note that, for the special case of a zero-length payload, the 2-byte
checksum is set to 0xFFFF. The checksum can only indicate the presence of one or more errors in the
payload. Unlike ECC, the checksum does not enable error correction. For this reason, checksum
calculation is not useful for some unidirectional DSI implementations since the peripheral has no way for
reporting errors to the host processor. Checksum generation and transmission is mandatory for host
processors sending long packets to peripherals. It is optional for peripherals transmitting long packets to
the host processor. However, the format of long packets is fixed; the peripherals that do not support
checksum generation should transmit two bytes having value 0x0000 in place of the checksum bytes
when sending long packets to the host processor. The host processor should disable checksum checking
for received long packets from peripherals that do not support checksum generation.
The checksum should be realized as a 16-bit CRC with a generator polynomial of x^16+x^12+x^5+x^0.
The LS byte is sent first, followed by the MS byte. Note that within the byte, the LS bit is sent first.
Figure 7-101. Checksum Transmission
The CRC implementation is presented in Figure 7-102 . The CRC shift register is initialized to 0xFFFF
1683 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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