Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1660 / 3738

Pixel to byte
packing formats
Data formats
Byte to pixel
unpacking formats
Data Control Data Control
Pixel Control
Pixel
8 bits 8 bits
Control
Application Application
Transmitter Receiver
Pixel Control Pixel Control
Low level protocol –
Lane management
layer
PHY layer
Packet-based protocol
Arbitrary data support
Lane distribution/lane merging
Generation/detection of packet start
and stop signaling
Serializer/deserializer
Clock generation/recovery (DDR)
Electrical layer
Low level protocol –
Lane management
layer
PHY layer
High-speed unidirectional clock
Lane 1 High-speed unidirectional data –
Data Control
Data Control Data Control
Data Control
Data Control
Data
N * 8 bits
8 bits
N * 8 bits
8 bits
Control
Lane N – High-speed unidirectional data
Video mode data stream of 16,18,
or 24 bits
Command mode stream
DSI
protocol
engine
DSI_PHY
dss-167
Lane 0 High-speed data (optionally bidirectional in LP mode) –
Public Version
Display Subsystem Functional Description
www.ti.com
Figure 7-88. DSI Transmitter/Receiver Data Flow
7.4.3.2 Clock Requirements
The serial clock generated by the DSI host and sent to the display can be a continuous clock. The clock
lane supports clock transmission even there is no data to send for displays that require continuous clock.
It is software programmed through the DSS.
DSI_CLK_CTRL [13] DDR_CLK_ALWAYS_ON bit: This bit
can be programmed only when the interface is disabled (that is, DSS. DSI_CTRL [0] IF_EN bit set to 0).
The peripheral can use two different kinds of clocks. The first one is the DDR clock provided on the clock
lane. The second clock is some transitions on the data lane 1 even if there is no valid data to send using
low power mode.
The LP clock (TxClkEsc) frequency provided to the DSI complex I/O is in the range of 67% to 150% of the
peripheral Low-Power (LP) clock frequency. It is generated internally by the DSI protocol engine module
using the DSI functional clock. The DSI functional clock is divided by 1, 2, 3, up to 8191 using the value
programmed in the DSS.
DSI_CLK_CTRL [12:0] LP_CLK_DIVISOR bit field. The LP clock generated from
DSI functional clock must be in the range of 20 MHz down to 32 KHz. The duty cycle must be 50/50
(tolerance of 45/55 for maximum value). LP clock frequency visible on the pads (DP xor DN) is half the
frequency of TxClkEsc.
The DSS. DSI_CLK_CTRL [20 ] LP_CLK_ENABLE bit is used to enable or disable the clock. When
disabled, the value of DSS. DSI_CLK_CTRL [12:0] LP_CLK_DIVISOR bit field is ignored and does not
have to be programmed by software users.
1660 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated