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Intel MCS48, User Manual

The Intel MCS48 is a powerful microcontroller series, offering exceptional functionality for various applications. Enhance your understanding of this product by accessing its comprehensive User Manual, available for free download at manualshive.com. Get the most out of your MCS48 experience with this informative manual.

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Summary of Contents for MCS48

Page 1: ...Im MCS 48 Family of Single Chip Microcomputers USER S MANUAL April 1979 Intel Corporation 1979 9800 2 70E ...

Page 2: ... 36 jps 6 RESET C 4 37 D PBs VDnC 5 36 D PB4 READY 6 35 U PB 3 io m C 34 DPB2 ior C 8 33 D pBi RD C 9 22 2 p iow C 10 8355 31 JPA7 ALEC 11 8755A 3 D PAS adq l 12 29 I PA6 fl0lC 13 28 J 4 AD2 14 i D PA3 AD3 E IB 23 JPA2 AD4 Q 16 25 3 i AD5 C 17 Z4 3 PAo AD6 I IB 23 3 Aio AD C 19 22 DAg vssC 20 21 H A8 PCj C 1 40 2 vcc pc C 2 39 2 PC2 TIMER IN C 3 36 2 PC RESET C 4 37 U pc pcs C 5 36 1 PBj TIMER OUT...

Page 3: ...Megachas sis MICROMAP MULTIBUS PROMPT RMX UPI uScope PROMWARE ICS and the combination of MCS ICE iSBC iCS or RMX with a numerical suffix Copyright 1 978 1 979 by Intel Corporation All rights reserved no part of this publication including any mnemonics contained herein may be reproduced without the prior written permission of Intel Corporation 3065 Bowers Avenue Santa Clara CA 95051 ...

Page 4: ...MOIXCVII ...

Page 5: ...tion Chapter 2 The Single Component MCS 48 System 8048 8748 8035 and 8049 8039 2 0 Summary 2 1 2 Architecture 2 1 2 2 Pin Description 2 14 2 3 Programming Verifying and Erasing EPROM 2 16 2 4 Test and Debug 2 18 8021 2 5 Program Memory 2 20 2 6 Data Memory 2 20 21 Oscillator and Clock 2 21 2 8 Timer Event Counter 2 21 2 9 Input Output Capabilities 2 22 2 10 CPU 2 24 2 1 Reset 2 24 8022 2 1 Program...

Page 6: ...trol Signal Summary 3 11 3 7 Port Characteristics 3 11 Chapter 4 Instruction Set 4 0 Introduction 4 1 Data Transfers 4 1 Accumulator Operations 4 2 Register Operations 4 2 Flags 4 2 Branch Instructions 4 2 Subroutines 4 3 Timer Instructions 4 3 Control 4 3 input Output Instructions 4 4 4 instruction Set Description 4 4 Summary 4 5 Symbols and Abbreviations 4 8 Alphabetic Listings by Mnemonic 4 9 C...

Page 7: ... 6 19 Microcomputers 6 28 Microcomputer 6 33 Microcomputer 6 36 I O Expander 6 42 Industrial Temperature 8243 6 48 ROM and I O Expander 6 54 EPROM and I O Expander 6 59 RAM and I O Expander 6 67 1024X 8 Bit Static RAM for MCS 85 6 81 Chapter 7 Compatible MCS 48 Components 2101A 8101A 4 1024 Bit Static MOS RAM with Separate I O 7 1 211 1A 4 1024 Bit Static MOS RAM with Common I O 7 5 2316E 16 384 B...

Page 8: ...8292 GPtB Controller 8 108 8294 Data Encryption Unit 8 110 8295 Dot Matrix Printer Controller 8 111 8041 8741 A Universal Peripheral Interface 8 Bit Microcomputer 8 112 Chapter 9 Support Products Model 220 Intellec Series 1 1 Microcomputer 9 1 Development System Model 230 Intellec Series 1 1 Microcomputer 9 5 Development System Intellec Prompt 48 MCS 48 Microcomputer 9 9 Design Aid ICE 49 MCS 48 I...

Page 9: ...Chapter 1 INTRODUCTION ...

Page 10: ...INTRODUCTION 1 0 Introduction to MCS 48 m 1 1 Functions of a Computer 1 5 1 2 Programming a Microcomputer 1 10 1 3 Developing An MCS 48 Based Product 1 13 ...

Page 11: ...S Megachas sis MICROMAP MULTIBUS PROMPT RMX UPI uScope PROMWARE ICS and the combination of MCS ICE iSBC iCS or RMX with a numerical suffix Copyright 1978 1979 by Intel Corporation All rights reserved no part of this publication including any mnemonics contained herein may be reproduced without the prior written permission of Intel Corporation 3065 Bowers Avenue Santa Clara CA 95051 ...

Page 12: ......

Page 13: ... System 1 15 Production 1 15 Chapter 2 The Single Component MCS 48 System 8048 8748 8035 and 8049 8039 2 0 Summary 2 1 2 1 Architecture 2 1 2 2 Pin Description 2 14 2 3 Programming Verifying and Erasing EPROM 2 16 2 4 Test and Debug 2 18 8021 2 5 Program Memory 2 20 2 6 Data Memory 2 20 2 7 Oscillator and Clock 2 21 2 8 Timer Event Counter 2 21 2 9 Input Output Capabilities 2 22 2 10 CPU 2 24 2 1 ...

Page 14: ...trol Signal Summary 3 11 3 7 Port Characteristics 3 11 Chapter 4 Instruction Set 4 0 Introduction 4 1 Data Transfers 4 1 Accumulator Operations 4 2 Register Operations 4 2 Flags 4 2 Branch Instructions 4 2 Subroutines 4 3 Timer Instructions 4 3 Control 4 3 Input Output Instructions 4 4 4 1 Instruction Set Description 4 4 Summary 4 5 Symbols and Abbreviations 4 8 Alphabetic Listings by Mnemonic 4 9...

Page 15: ...22 Microcomputer 6 36 8243 I O Expander 6 42 I8243 Industrial Temperature 8243 6 48 8355 ROM and I O Expander 6 54 8755 EPROM and I O Expander 6 59 8155 56 RAM and I O Expander 6 67 8185 8185 2 1024X 8 Bit Static RAM for MCS 85 6 81 Chapter 7 Compatible MCS 48 Components 2101 A 8101 A 4 1024 Bit Static MOS RAM with Separate I O 7 1 211 1A 4 1024 Bit Static MOS RAM with Common I O 7 5 2316E 16 384 ...

Page 16: ...8292 GPIB Controller 8 108 8294 Data Encryption Unit 8 110 8295 Dot Matrix Printer Controller 8 111 8041 8741A Universal Peripheral Interface 8 Bit Microcomputer 8 112 Chapter 9 Support Products Model 220 Intellec Series 1 1 Microcomputer 9 1 Development System Model 230 Intellec Series 1 1 Microcomputer 9 5 Development System Intellec Prompt 48 MCS 48 Microcomputer 9 9 Design Aid ICE 49 MCS 48 In...

Page 17: ...Chapter 1 INTRODUCTION ...

Page 18: ...INTRODUCTION 1 0 Introduction to MCS 48 1 1 1 1 Functions of a Computer 1 5 1 2 Programming a Microcomputer 1 10 1 3 Developing An MCS 48 Based Product 1 13 ...

Page 19: ...cessors The 8048 is however a true low cost microcomputer A single 5V supply re quirement for all MCS 48 components assures that low cost also applies to the power supply in your system New Family Members The MCS 48 family of microcomputers which began with the 8048 and 8748 has now been expanded with new members which provide either more capability or lower cost than the original family mem bers ...

Page 20: ...For such applications as Keyboards Dis plays Serial communication lines etc standard MCS 80 85 peripheral circuits may be added Program and data memory may be expanded using standard memories or the 8355 and 8155 memories that also include programmable I O lines and timing functions For applications which require a more custom tailored interface the 8041 or 8741 Universal Peripheral Interface UPI ...

Page 21: ...Erasable able 2732 4K x 8 450 ns Light Erasable Standard RAMs 2111A 4 256 x 4 450 ns Common I O Data memory can be easily ex co 1 2101A 4 256 x 4 450 ns Separate I O panded using standard NMOS 5101 256x4 650 ns CMOS RAMs The 5101 CMOS equiva Ul lent reduces standby power to 75 z o 0 s nW bit Standard I O 8212 8 Bit I O Port Serves as Address Latch or I O o o port s 8255A Programmable Peripheral In...

Page 22: ...he 8048 and 8049 in various combinations with the Intel 8355 8755 Program Memory and I O Expander and the 8155 Data Memory and I O Expander Data Memory can be expanded beyond the resident words in blocks of 256 by adding 8155 s Program Memory can be expanded beyond the resident 1K or 2K in blocks of 2K by using the 8355 8755 in com bination with the 8048 or 8049 If all external memory is desired t...

Page 23: ...to the outside world The output may go to a display for use by a human operator to a peripheral device that produces hard copy such as a line printer to a peripheral storage device such as a floppy disk unit or the output may constitute process control signals that direct the operations of another system such as an automated assembly line Like input ports output ports are addressable The input and...

Page 24: ... this kind of jump the processor is required to remember the contents of the program counter at the time that the jump occurs This enables the processor to resume execution of the main program when it is finished with the last instruction of the subroutine A Subroutine is a program within a program Usually it is a general purpose set of instructions that must be executed repeat edly in the course ...

Page 25: ...presents a set of activities associated with execution of a particular instruction code The enabled line can be combined with selected timing pulses to develop electrical signals that can then be used to initiate specific actions This translation of code into action is performed by the Instruction Decoder and by the associated control circuitry An 8 bit instruction code is often sufficient to spec...

Page 26: ...tions required fetches the next instruction and so on This orderly sequence of events requires precise timing and the CPU therefore requires a free running oscillator clock which furnishes the reference for all processor actions The combined fetch and execution of a single instruction is referred to as an Instruction Cycle The portion of a cycle identified with a clearly defined activity is called...

Page 27: ...tral processors as a means of improving the processor s efficiency Consider the case of a computer that is processing a large volume of data portions of which are to be output to a printer The CPU can output a byte of data within a single machine cycle but it may take the printer the equivalent of many machine cycles to actually print the char acter specified by the data byte The CPU could then re...

Page 28: ...t and efficient code possible The following is an example of a machine language program This program reads 5 sequential 8 bit words in from an I O port and stores them sequentially in data memory The program starts by initializing two registers one which determines where the data is to be stored and another which counts the number of words to be stored When finished the processor continues on to t...

Page 29: ...branch addresses and other operands For example the instruction to increment the contents of register becomes INC R0 instead of the hex 18 giving the user at a glance the meaning of the instruction Our example program can be written in assembly language as follows Step No Hex Code Assembly Code B8 1 20 2 BA 3 05 4 09 5 AO 6 18 7 EA 8 04 MOV R0 32 MOV R2 05 INP IN A P1 MOV R0 A INC R0 DJNZ R2 INP T...

Page 30: ...ediate data of this instruction to be defined in a single statement and eliminated the need for a third symbol equal to ALFA BETA 2 2 Conditional Assembly Conditional as sembly allows the programmer to select only certain portions of his assembly language source program for conversion to machine object code at assembly time This allows for instance the inclusion of various debug routines to be inc...

Page 31: ... more specific applications routines 1 3 2 Function Definition After a thorough understanding of the microprocessor is achieved the functions to be implemented can be defined using a flowchart method to describe each basic system function and the sequence in which the processor executes these functions Once the system is flowcharted critical time related functions can be identified and sample prog...

Page 32: ... PROMPT 48 one for programming the 8748 and one in which a programmed 8748 executes its program while under control of the monitor routine Use of PROMPT 48 involves the following steps 1 Loading an application program into the PROMPT RAM memory via Hex keyboard or external terminal TTY and RS232 interface provided 2 Inserting an erased 8748 in the program ming socket and transferring the applicati...

Page 33: ...rious optional modules The macro assembler and text editor programs provided allow the designer to write and edit his programs in assembly language and then generate the machine language output necessary to program the 8748 EPROM The availability of a high speed CRT and a diskette operating system eliminates the laborious input and output of paper tape files normally required during the assembly p...

Page 34: ......

Page 35: ...Chapter 2 ...

Page 36: ... 5 Program Memory 2 20 2 6 Data Memory 2 20 2 7 Oscillator and Clock 2 21 2 8 Timer Event Counter 2 21 2 9 Input Output Capabilities 2 22 2 10 CPU 2 24 2 1 1 Reset 2 24 SECTION 3 8022 2 12 Program Memory 2 25 2 13 Data Memory 2 25 2 14 Oscillator and Clock 2 26 2 15 Timer Event Counter 2 26 2 16 Input Output 2 26 2 1 7 Test and Interrupt Inputs 2 27 2 18 Analog to Digital Converter 2 28 2 19 CPU 2...

Page 37: ...on is stored in the Instruction Decoder and converted to outputs which control the function of each of the blocks of the Arithmetic Section These lines control the source of data and the destination register as well as the function performed in the ALU Arithmetic Logic Unit The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under control of the Instruction Decod...

Page 38: ...SINGLE COMPONENT SYSTEM o z g Q z O 2 o 1 D O ID t U t S3 1 CC t UJ o CC CC CC 300030 Zoc 8048 8049 BLOCK DIAGRAM 2 2 ...

Page 39: ...array In addition the first 8 locations 0 7 of the array are designated as working registers and are directly addressable by several instructions Since these registers are more easily addressed they are usually used to store frequently accessed intermediate results The DJNZ instruction makes very efficient use of the working registers as pro gram loop counters by allowing the programmer to decreme...

Page 40: ...s are grouped as 3 ports of 8 lines each which serve as either inputs outputs or bidirectional ports and 3 test inputs which can alter program sequences when tested by conditional jump instructions Ports 1 and 2 Ports 1 and 2 are each 8 bits wide and have identical characteristics Data written to these ports is statically latched and remains un changed until rewritten As input ports these lines ar...

Page 41: ... Three pins serve as inputs and are testable with the conditional jump instruction These are TO T1 and INT These pins allow inputs to cause program branches without the neces sity to load an input port into the accumulator The TO T1 and INT pins have other possible functions as well See the pin description in Sec 2 2 2 1 6 Program Counter and Stack The Program Counter is an independent counter whi...

Page 42: ...er four bits of PSW are stored in the Program Counter Stack with every call to subroutine or interrupt vector and are optionally restored upon return with the RETR instruction The RET return instruction does not update PSW The PSW bit definitions are as follows Bits 0 2 Stack Pointer bits S S S 2 Bit 3 Not used 1 level when read Working Register Bank Switch Bit BS Bank 1 Bank 1 Flag bit F0 user co...

Page 43: ...cation 3 in program memory as soon as all cycles of the current instruction are complete As in any CALL to subroutine the Program Counter CONDITIONAL JUMP LOGIC TIMER INT_ RECOGNIZED EXECUTED EN TCNTI EXECUTED DIS TCNTI EXECUTED L TIMER INT ENABLE r O EXTERNAL INTERRUPT RECOGNIZED TIMER INTERRUPT RECOGNIZED S Q INTERRUPT IN PROGRESS FF A RETR EXECUTED NOTE 1 INT INPUT IS SAMPLED BY ALE EVERY MACHI...

Page 44: ...ated by the service subroutine to reset the interrupt request The INT pin may also be tested using the conditional jump instruction JNI This instruction may be used to detect the presence of a pending interrupt before interrupts are enabled If interrupt is left disabled INT may be used as another test input like TO and T1 2 1 10 Timer Counter The 8048 contains a counter to aid the user in counting...

Page 45: ... xsec assuming 6 MHz XTAL Various delays between 80 usee and 20 msec 256 counts can be obtained by presetting the counter and detecting overflow Times longer than 20 msec may be achieved by accumulating mul tiple overflows in a register under software control For time resolution less than 80 sec an external clock can be applied to the T1 input and the counter operated in the event counter mode ALE...

Page 46: ...vided by 5 in the Cycle Counter to provide a clock which defines a machine cycle consisting of 5 machine states This clock is called Address Latch Enable ALE because of its function in MCS 48 systems with external memory It is provided continu ously on the ALE output pin 2 1 12 Reset The reset input provides a means for initializa tion for the processor This Schmitt trigger input has an internal p...

Page 47: ... 3 Q 1 D 3 Q 1 O 3 O 1 3 ui iE So 4 z O J 1 1 1 1 1 u CO 1 1 1 1 1 1 1 3 O PS g 8 P5 u 1 1 1 0 a o O O a cc X cc tt CC 01 tt tt CC E E CC cc E tt tt tt CC E K 1 H H h t H H K H 1 z 1 z z 1 z t z V z 1 Z 1 Z Z H Z 5 z u z z 5 Z Z z r z t 2 t z Z 3 Z 3 z Z3 Z 3 Z D Z 3 Z D Z 3 Z 3 Z 3 3 2 S Z CM s8 18 s8 18 s8 18 in o 2 s8 18 s8 S8 s8 i 5 O 2 U So 28 28 s8 18 cS k 2 z tt tt s S S c S 5 Ss S is Si S ...

Page 48: ...he processor responds by stopping during the instruction fetch portion of the next instruction If a double cycle instruc tion is in progress when the single step com mand is received both cycles will be com pleted before stopping 3 The processor acknowledges it has entered the stopped state by raising ALE high In this state which can be maintained indefinitely the address of the next instruc tion ...

Page 49: ... RAM array for low power standby operation In the power down mode the contents of data RAM can be maintained while drawing typically 10 to 15 of normal operating power requirements Vcc serves as the 5V supply pin for the bulk of 8048 circuitry while the Vdd pin supplies only the RAM array In normal operation both pins are at 5V while in standby Vcc is at ground and only Vqd is maintained at 5V App...

Page 50: ...rnal Access Mode Normally the first 1K 8048 or 2K 8049 words of program memory are automati cally fetched from internal ROM or EPROM The EA input pin however allows the userto effectively disable internal program mem ory by forcing all program memory fetches to reference external memory The follow ing chapter explains how access to external program memory is accomplished The External Access mode i...

Page 51: ...tten or read syn chronously using the RD WR strobes The port can also be statically latched Contains the 8 low order program counter bits during an external program memory fetch and receives the ad dressed instruction under the control of PSEN Also con tains the address and data during an external RAM data store instruction under control of ALE RD and WR Input pin testable using the conditional tr...

Page 52: ...nal pullup 10MO on 8048 8049 8035L 8039 only One side of crystal input for internal oscillator Also input for external source Other side of crystal external source input Unless otherwise stated inputs do not have internal pullup resistors 2 3 Programming Verifying and Erasing EPROM The internal Program Memory of the 8748 may be erased and reprogrammed by the user as explained in the following sect...

Page 53: ...at constant exposure to room level fluorescent lighting could erase the typical 8748 in approximately 3 years while it would take approximately 1 week to cause erasure when exposed to direct sunlight If the 8748 is to be exposed to these types of lighting conditions for extended periods of time opaque labels are available from Intel which should be placed over the 8748 win dow to prevent unintenti...

Page 54: ...ress of the next instruction to be fetched available on the eight lines of BUS and the lower 4 bits of port 2 P23 P22 P21 P20 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO An Aio 9 ADDRESS OUTPUT DURING SINGLE STEP This allows the user to step through his program and note the sequence of instruc tions being executed While the processor is stopped the I O information on BUS and the 4 bits of port 2 is of course ...

Page 55: ...L levels of BUS and Port 2 which output the address during single step see below The address is latched by a 0 to 1 transitio n on RESET and a high level on RESET causes the contents of the program memory location addressed to appear on the eight lines of BUS RESET must be brought back to 0V before leaving the READ mode 8048 8748 DB7 DB6 DB5 DB4 DB3 DB2 ALE TO l Oo DIEN CS T l Oo DIEN CS Aio 8049 ...

Page 56: ...not be preset in the IRAR when selected by an indirect register instruction IRAR s may point to address 0 7 if desired Locations 8 23 may be used as the address stack The address stack enables the pro cessor to keep track of the return addresses generated from CALL instructions A 3 bit stack pointer SP supplies the address of the locations to be loaded with the next return address generated The SP...

Page 57: ...e may vary and should be adjust ed as necessary The 8021 utilizes dynamic RAM and certain other dynamic logic Due to the clocking required with dynamic circuits the oscil lator frequency must be equal to or greater than 600K Hz or improper operation may occur 2 8 Timer Event Counter The 8021 has internal timer event counter circuits that can monitor elapsed time or count external events that occur...

Page 58: ...gurations are highly flexible A number of different configur ations are possible tailoring an 8021 to a given task Other than the power supply and dedicated pins all other pins 20 can be used for input output or both depending on the configuration All ports are quasi bidirectional to facili tate stand alone use A simplified sche matic of the quasi bidirectional inter face is shown in Figure 3 This...

Page 59: ... required to do high power control P10and P11 have been designated high drive outputs capable of sinking 7mA at Vss 2 5 volts For clarity this is 7mA to Vss with a 2 5 volt drop across the buffer These pins may of course be paralleled for 14mA drive if the output logic states are always the same 2 9 3 Expanded I O The 8021 can be used with the 8243 I O expander chip which provides additional I O c...

Page 60: ...sing the DAA SWAP A and XCHD instructions In addition MOVP A A allows table lookup for display formating and constants The conditional branch logic within the processor enables several conditions inter nal and external to the processor to be tested by the users program Use the conditional jump instructions with the tests listed below to effect a change in the program execution sequence Test Jump J...

Page 61: ...able by any of the 1 1 direct register instructions These locations are readily accessi ble for a variety of operations with a minimum num ber of instruction bytes required for their manipulation Thus they are usually used to store frequently accessed intermediate results The DJNZ instruction makes very efficient use of the working registers as program loop counters by al lowing the programmer to ...

Page 62: ... the 8022 has an internal timer event counter This circuit can monitor elapsed time or count external events that occur during program execution See the 8021 description Section 2 8 for a com plete explanation The 8022 has 26 lines which can be used for digi tal input or output functions These lines are orga nized as 3 ports of 8 lines each of which serve as either inputs outputs or bidirectional ...

Page 63: ...ble input An interrupt se quence is initiated by applying a low 0 level input to the TO pin when external interrupt is enabled Interrupt is level triggered and active low to allow WIRE ORING of several interrupt sources at the input pin When an interrupt is detected it causes a jump to subroutine at location 3 in program memory as soon as all other cycles of the current instruction are complete At...

Page 64: ... on high to low transitions This change was made on the 8022 to take advantage of the accuracy of the rising edge detection on the zero cross circuitry The maximum rate at which the counter may be incremented is once per three instruction cycles every 30 jus when using a 3 MHz crystal there is no minimum frequency In addition to serving as a testable input and as the counter input the T1 pin has s...

Page 65: ...provide the analog input signal no later than the beginning of the select in struction cycle The analog input is then sampled by the A D converter and maintained internally This voltage becomes one input to the voltage comparator which amplifies the difference be tween the analog input and the voltage tap on the series resistor string The series resistor string is connected between the A D referen...

Page 66: ...BCD arithmetic capability using the DAA SWAP A and XCHD instructions In addition MOVP A A allows table lookup for display formating and constants The conditional branch logic within the processor enables several conditions internal and external to the processor to be tested by the user s program Use the conditional jump instruc tions with the tests listed below to effect a change in the program ex...

Page 67: ......

Page 68: ...ystems 3 9 3 5 Memory Bank Switching 3 10 3 6 Control Signal Summary 3 11 3 7 Port Characteristics 3 11 MCS 48 CYCLE TIMING FOR EXTERNAL MEMORY ALE PSEN 1 1 L J PC ADDRESS PC o N ADDRESS N IF M 1 EXTERNAL PROGRAM EMORY FETCH BUS INSTRUCTIO INSTRUCTIC ADDRESS WRITE READ PORT I O 2023 Y ADDRESS Y PORT I O Y ADDRESS Y PORT I O PC IF EXTERNAL PROGRAM MEMORY FETCH RD r WR r ...

Page 69: ...abilities to the application Both expander devices and standard mem ories and peripherals can be added in virtually any number and combination required 3 1 Expansion of Program Memory Program Memory is expanded beyond the resident 1K or 2K words by using the 8085 BUS feature of the MCS 48 All program memory fetches from addresses less than 1024 2048 occur internally with no external signals being ...

Page 70: ...ruction Interrupt service routines should therefore be contained A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A i I Conventional Program Counte Counts 000H to 7FFH Overflows 7FFH to 000H r internal flipflop to An Flipflop set by SEL MB1 Flipflop reset by SEL MBO or by RESET During interrupt service routine Aii is forced to 0 All 12 bits are saved in stack PROGRAM COUNTER entirely in the lower 2K words of pr...

Page 71: ...lect input If the system requires only 2K of program the same configuration can be used with an 8035 substituted for the 8048 The 8049 would provide 4K with the same configuration The next figure shows how the new 8755 8355 EPROM ROM with I O interfaces directly to the 8048 without the need for an address latch The 8755 8355 contains an internal 8 bit address latch eliminating the need for an 8212...

Page 72: ...ite Cycle All address and data is transferred over the 8 lines of BUS A read or write cycle occurs as follows 1 The contents of register R0 or R1 is out puted on BUS 2 Address Latch Enable ALE indicates address is valid The trailing edge of ALE is used to latch the address externally 3 A read RD or write WR pulse on the corresponding output pins of the 8048 indi cates the type of data memory acces...

Page 73: ... of the memories while the data bus output drivers of the memories are con trolled by RD The chip select lines of the memories are continuously enabled unless additional pages of RAM are required Also shown is the expansion of data memory using the 8155 memory and I O expanding device Since the 8155 has an internal 8 bit address latch it can interface directly to the 8048 with out the use of an ex...

Page 74: ...4 OR Accumulator to Port A 4 bit transfer from a port to the lower half of the Accumulator sets the most significant four bits to zero All communication between the 8048 and the 8243 occurs over Port 2 lower P20 P23 with timing provided by an output pulse on the PROG pin of the processor Each transfer consists of two 4 bit nibbles The first containing the op code and port address and the second co...

Page 75: ...rogram and data memory expansion the 8355 8755 and 8155 expanders also contain I O capability 8355 8755 These two parts are ROM and EPROM equivalents and therefore contain the same I O structure I O consists of two 8 bit ports which normally reside in the exter nal data memory address space and are ac cessed with MOVX instructions Associated with each port is an 8 bit Data Direction Reg ister whic...

Page 76: ...s and a decoder could also be used to address the four chips Large numbers of 8243 s would require a chip select decoder chip such as the 8205 to save I O pins Also shown is the 8048 interface to a stan dard MCS 80 peripheral in this case the 8255 Programmable Peripheral Interface a 40 pin part which provides three 8 bit pro grammable I O ports The 8255 bus interface is typical of programmable MCS...

Page 77: ... an output port with ad dress information prior to executing a MOVX instruction 3 4 Multi Chip MCS 48 Systems The accompanying figure shows the addition of two memory expanders to the 8048 one 8355 8755 ROM and one 8156 RAM The main consideration in designing such a sys tem is the addressing of the various memories and I O ports Note that in this configuration address lines A10 and An have been OR...

Page 78: ...equire more than the 4K words of program memory which are directly addressable by the program counter or more than the 256 data memory and I O locations directly addressable by the pointer registers R0 and R1 These systems can be achieved using bank switching techniques Bank switching is merely the selection of various blocks or banks of memory using dedicated output port lines from the processor ...

Page 79: ...ded for use in the single chip configuration where BUS is not being used as an expan der port OUTL and MOVX instructions can be mixed if necessary However a previous ly latched output will be destroyed by exe cuting a MOVX instruction and BUS will be left in the high impedance state INS does not put the BUS in a high impedance state Therefore the use of MOVX after OUTL to put the BUS in a high imp...

Page 80: ...ION CAPABILITY 8049 8048 8748 8035 8039 v c b I O LZ 8355 8755 ROM I O 2Kx8 H 0 en x 1 i 22 8155 RAM I O 256x8 II ADDRESS LATCH 1 8251 USART SERIAL SERIAL OUTPUT INPUT STANDARD ROM EPROM HI 8279 KEYBOARD DISPLAY 7 STANDARD RAM It DDD 3 12 ...

Page 81: ...Chapter 4 INSTRUCTION SET ...

Page 82: ...INSTRUCTION SET 4 0 Introduction 4 1 4 1 Instruction Set Description 4 4 ...

Page 83: ...handle arithmetic operations in both binary and BCD as well as to efficiently handle the single bit operations required in control applications Special instructions have also been in cluded to simplify loop counters table lookup routines and N way branch rou tines Data Transfers As can be seen in the accompanying diagram the 8 bit accumulator is the central PROGRAM MEMORY data EXPANDER I O PORTS 4...

Page 84: ...Adjust instruction is included This instruction is used to correct the result of the binary addition of two two digit BCD numbers Performing a decimal adjust on the result in the accumulator produces the required BCD result Finally the accumulator can be incre mented decremented cleared or comple mented and can be rotated left or right 1 bit at a time with or without carry Although there is no sub...

Page 85: ... allows the program to be vectored to any one of several different locations based on the contents of the accumulator The contents of the accumulator points to a location in program memory which contains the jump address The 8 bit jump address refers to the current page of execution This instruction could be used for instance to vector to any one of several routines based on an ASCII character whi...

Page 86: ... of BUS must be treated as either input or output at any one time In addition to being a static port BUS can be used as a true synchronous bi directional port using the Move External instructions used to access external data memory When these instructions are executed a cor responding READ or WRITE pulse is generated and data is valid only at that time When data is not being transferred BUS is in ...

Page 87: ... 2 2 JNZaddr Jump on A not Zero 2 2 JTO addr Jump on TO 1 2 2 n JNTO addr Jump on TO 2 2 m JT1 addr Jump on T1 1 2 2 JNT1 addr Jump on T1 2 2 JFOaddr Jump on F0 1 2 2 JF1 addr Jump on F1 1 2 2 JTF addr Jump on timer flag 1 2 2 JNI addr Jump on INT 2 2 JBbaddr Jump on Accumulator Bit 2 2 Description Bytes Cycles CALL addr Jump to subroutine 2 2 3 O RET Return 1 2 SI 3 CO RETR Return and restore sta...

Page 88: ...C addr Jump on Carry 1 2 2 JNC addr Jump on Carry 2 2 JZ addr Jump on A Zero 2 2 JNZ addr Jump on A not Zero 2 2 JT1 addr Jump on T1 1 2 2 JNT1 addr Jump on T1 2 2 JTF addr Jump on timer flag 2 2 CALL addr RET Jump to subroutine Return No Operation Instruction Set The following instructions which are found in the 8748 have been deleted from the 8021 instruction set Data Moves Registers Branch Time...

Page 89: ...1978 Description Hexadecimal Bytes Cycle Opcode JTO JNTO JT1 addr JNT1 addr JTF addr Jump on T0 1 Jump on T0 0 Jump on T1 1 Jump on T1 0 Jump on timer flag 2 2 36 2 2 26 2 2 56 2 2 46 CALL addr Jump to subroutine o RET Return g CLR C r CPL C Clear carry Complement carry MOV A Rr MOV A R MOV A data MOV Rr A MOV R A MOV R r data a o MOV R data Move register to A Move data memory to A Move immediate ...

Page 90: ...r Expression DBF Memory Bank Flip Flop FO F1 Flag 0 Flag 1 I Interrupt P Mnemonic for in page Operation PC Program Counter Pp Port Designator p 1 2 or 4 7 PSW Program Status Word Rr Register Designator r 0 1 or 0 7 SP Stack Pointer T Timer TF Timer Flag TO T1 Test 0 Test 1 X Mnemonic for External RAM Immediate Data Prefix Indirect Address Prefix Current Value of Program Counter X Contents of X X C...

Page 91: ... HEX TO REG ADD VALUE OF LOCATION 31 TO ACC ADD A data Add Immediate Data to Accumulator 00 00 11 d7ded5 d4 d3d2d do This is a 2 cycle instruction The specified data is added to the accumulator Carry is affected A A data Example ADDID ADD A ADDER ADD VALUE OF SYMBOL ADDER TO ACC ADDC A Rr Add Carry and Register Contents to Accumulator 111 1 r r r The content of the carry bit is added to accumulato...

Page 92: ...to accumulator location and the carry bit cleared Then the specified data is added to the accumulator Carry is affected A A data C ADDC A 225 ADD CARRY AND 225 DEC TO ACC Example ANL A Rr Logical AND Accumulator With Register Mask 0101 1 r r r Data in the accumulator is logically ANDed with the mask contained in working register r A A AND Rr ANDREG ANL A R3 r 0 7 Example ANL A Rr Logical AND Accum...

Page 93: ...mask This instruction assumes prior specification of an OUTL BUS A instruction BUS BUS AND data Example ANDBUS ANL BUS MASK AND BUS CONTENTS WITH MASK EQUAL VALUE OF SYMBOL MASK ANL Pp data Logical AND Port 1 2 With Immediate Mask Not in 8021 8022 100 1 1 Op p d7d 6 d 5 d 4 d 3 d 2 d o This is a 2 cycle instruction Data on port p is logically ANDed with an immediately specified mask Example Pp Pp ...

Page 94: ...r 4094 4095 Execution continues at the instruction following the CALL upon return from the subroutine SP PC PSW 4_ 7 SP SP 1 PC8 10 addr 8 10 PC 7 addrn 7 PCnJ DBF Example Add three groups of two numbers Put subtotals in locations 50 51 and total in location 52 MOV R0 50 BEGADD MOV A R1 ADD A R2 CALL SUBTOT ADD A R3 ADD A R4 CALL SUBTOT ADD A R5 ADD A R6 CALL SUBTOT SUBTOT MOV R0 A INC R0 RET MOVE...

Page 95: ...21 8022 1000 10 1 Flag is cleared to zero F0 0 CPL A Complement Accumulator 00 11 111 The contents of the accumulator are complemented This is strictly a one s complement Each one is changed to zero and vice versa A NOT A Example Assume accumulator contains 01101010 CPLA CPL A ACC CONTENTS ARE COMPLE MENTED TO 10010101 CPL C Complement Carry Bit 10 10 111 The setting of the carry bit is complement...

Page 96: ...owing the binary addition of BCD numbers The carry bit C is affected If the contents of bits 0 3 are greater than nine or if AC is one the accumulator is incremented by six The four high order bits are then checked If bits 4 7 exceed nine or if C is one these bits are increased by six If an overflow occurs C is set to one Example Assume accumulator contains 10011011 DA A ACC ADJUSTED TO 00000001 W...

Page 97: ...e Timer Counter Interrupt Not in 8021 00 11 10 1 Timer counter interrupts are disabled Any pending timer interrupt request is cleared The interrupt sequence is not initiated by an overflow but the timer flag is set and time accumulation continues DJNZ Rr address Decrement Register and Test 1110 1 r r r a7 a6 a 5 a4 a3 a2 a a This is a 2 cycle instruction Register Y is decremented and tested for ze...

Page 98: ...le External Interrupt Not in 8021 000 10 1 External interrupts are enabled A low signal on the interrupt input pin initiates the interrupt sequence EN TCNTI Enable Timer Counter Interrupt Not in 8021 00 10 10 1 Timer counter interrupts are enabled An overflow of the timer counter initiates the interrupt sequence ENT0 CLK Enable Clock Output Not in 8021 8022 111 10 1 The test pin is enabled to act ...

Page 99: ... R0 A INC Rr Increment Register MOVE 100 DEC TO ADDRESS REG MOVE CONTENTS OF LOCATION 100 TO ACC INCREMENT A MOVE ACC CONTENTS TO LOCATION 100 00 1 1 r r r The contents of working register Y are incremented by one Rr Rr 1 r 0 7 Example INCR0 INC R0 INCREMENT ADDRESS REG INC Rr Increment Data Memory Location 000 1 00 r The contents of the resident data memory location addressed by register Y bits 0...

Page 100: ...tion Control passes to the specified address if accumulator bit b is set xo one b 0 7 PC0 7 addr PC PC 2 If Bb 1 If Bb 0 Example JB4IS1 JB4 NEXT JC address Jump If Carry Is Set JUMP TO NEXT ROUTINE IF ACC BIT 4 1 1111 110 a7 a 6 a 5 a4 a3 a 2 a a This is a 2 cycle instruction Control passes to the specified address if the carry bit is set to one PC0 7 addr PC PC 2 If C 1 If C 0 Example JC1 JC OVFL...

Page 101: ...n PC8 io PC0 7H PCn addr 8 10 addr 0 7 DBF Example JMP SUBTOT JMP 6 JMP 2FH JUMP TO SUBROUTINE SUBTOT JUMP TO INSTRUCTION SIX LOCATIONS BEFORE CURRENT LOCATION JUMP TO ADDRESS 2F HEX JMPP A Indirect Jump Within Page 1011 0011 This is a 2 cycle instruction The contents of the program memory location pointed to by the accumulator are substituted for the page portion of the program counter PC bits 0 ...

Page 102: ...a 6 a 5 a 4 a 3 a 2 a a This is a 2 cycle instruction Control passes to the specified address if the test signal is low PC 7 addr PC PC 2 If T0 0 If T0 1 Example JT0LOW JNT0 60 JNT1 address Jump If Test 1 Is Low JUMP TO LOCATION 60 DEC IF T0 0 100 110 a7 a 6 a 5 a 4 a3 a 2 a a This is a 2 cycle instruction Control passes to the specified address if the test 1 signal is low PCo 7 addr PC PC 2 If T1...

Page 103: ...dress nstruction Control if the test signal passes to the s high 1 pCo 7 addr PC PC 2 If T0 1 If T0 0 Example JT0HI JT0 53 JUMP TO LOCATION 53 DEC IFT0 1 JT1 address Jump If Test 1 Is High 10 1 110 a7 a 6 a 5 a4 a 3 a 2 a a This is a 2 cycle i specified address nstruction Control if the test 1 signal passes to the is high 1 PC 7 addr PC PC 2 If T1 1 If T1 0 Example JT1HI JT1 COUNT JZ address Jump ...

Page 104: ...MOV A PSW JB4RB1SET MOVE PSW CONTENTS TO ACC JUMP TO RB1SET IF ACC BIT 4 1 MOV A Rr Move Register Contents to Accumulator 1111 1 r r r 8 bits of data are moved from working register r into the accumulator A Rr MAR MOV A R3 r 0 7 Example MOV A Rr Move Data Memory Contents to Accumulator MOVE CONTENTS OF REG 3 TO ACC 1111 OOOr The contents of the resident data memory location addressed by bits 0 5 o...

Page 105: ... All condition bits and the stack pointer are affected by this move PSW A Example Move up stack pointer by two memory locations that is increment the pointer by one INCPTR MOV A PSW INC A MOV PSW A MOVE PSW CONTENTS TO ACC INCREMENT ACC BY ONE MOVE ACC CONTENTS TO PSW MOV Rr A Move Accumulator Contents to Register 10 10 1 r r r The contents of the accumulator are moved to register r Rr A MRA MOV R...

Page 106: ...V Rr data Move Immediate Data to Data Memory 10 11 000 r d7 6q d 5 d4 d3d2d do This is a 2 cycle instruction The 8 bit value specified by data is moved to the resident data memory location addressed by register r bits 0 5 Rr data r 0 1 Examples Move the hexadecimal value AC3F to locations 62 63 MIDM MOV R0 62 MOV R0 0ACH INC R0 MOV R0 3FH MOVE 62 DEC TO ADDR REG MOVE AC HEX TO LOCATION 62 INCREMEN...

Page 107: ...3 port p Accumulator bits 4 7 are unaffected See NOTE above regarding port mapping Pp A _ 3 p 4 7 Example Move data in accumulator to ports 4 and 5 OUTP45 MOVD P4 A SWAP A MOVD P5 A MOVE ACC BITS 0 3 TO PORT 4 EXCHANGE ACC BITS 0 3 AND 4 7 MOVE ACC BITS 0 3 TO PORT 5 MOVP A A Move Current Page Data to Accumulator 10 10 00 11 The contents of the program memory location addressed by the accumulator ...

Page 108: ... always reset MOVE B8 HEX TO ACC 10111000 LOGICAL AND ACC TO MASK BIT 7 00111000 MOVE CONTENTS OF LOCATION 38 HEX IN PAGE 3 TO ACC ASCII 8 Access contents of location in page 3 labelled TAB1 Assume current program location is not in page 3 TABSCH MOV A LOW TAB1 ISOLATE BITS 0 7 OF LABEL ADDRESS VALUE MOVP3 A A MOVE CONTENTS OF PAGE 3 LOCATION LABELED TAB1 TO ACC MOVX A Rr Move External Data Memory...

Page 109: ...ulator is logically ORed with the mask contained in working register Y A A OR Rr ORREG ORL A R4 r 0 7 Example ORL A Rr Logical OR Accumulator With Memory Mask OR ACC CONTENTS WITH MASK IN REG 4 100 OOOr Data in the accumulator is logically ORed with the mask contained in the resident data memory location referenced by register Y bits 0 5 A A OR Rr Example ORDM MOV R0 3FH ORL A R0 r 0 1 MOVE 3F HEX...

Page 110: ...00 1 1 pp This is a 2 cycle instruction Data on port p is logically ORed with the digit mask contained in accumulator bits 0 3 Pp Pp OR Ao_g p 4 7 Example ORP7 ORLD P7 A OR PORT 7 CONTENTS WITH ACC BITS 0 3 OUTL P0 A Output Accumulator Data to Port 8021 8022 Only 1001 0000 OUTL BUS A Output Accumulator Data to BUS Not in 8021 8022 0000 00 10 This is a 2 cycle instruction Data residing in the accum...

Page 111: ...22 Only 1000 00 00 This is a two cycle instruction The contents of the A D conversion result register are moved to the accumulator A CRR RET Return Without PSW Restore 10 00 00 11 This is a 2 cycle instruction The stack pointer PSW bits 0 2 is decremented The program counter is then restored from the stack PSW bits 4 7 are not restored SP SP 1 PC SP RETI Return From Interrupt 8022 Only 100 1 00 11...

Page 112: ...e contents of the accumulator are rotated left one bit Bit 7 is rotated into the bit position An 1 An A0 A7 n 0 6 Example Assume accumulator contains 10110001 RLNC RL A NEW ACC CONTENTS ARE 01100011 RLC A Rotate Left Through Carry Example 1111 111 The contents of the accumulator are rotated left one bit Bit 7 replaces the carry bit the carry bit is rotated into the bit position n 0 6 An 1 An A0 C ...

Page 113: ...nts of the accumulator are rotated right one bit Bit replaces the carry bit the carry bit is rotated into the bit 7 position n 0 6 An An 1 A7 C C A Assume carry is not set and accumulator contains 10110001 RRTC RRC A CARRY IS SET AND ACC CONTAINS 01011000 SEL ANO Select Analog Input Zero 8022 Only 100 1 010 1 SEL AN1 Select Analog Input One 8022 Only 1000 10 1 One of the two analog inputs to the A...

Page 114: ...rences to working registers 0 7 address data memory locations 0 7 This is the recommended setting for normal program execution BS SEL RB1 Select Register Bank 1 Not in 8021 8022 110 1 10 1 PSW bit 4 is set to one References to working registers 0 7 address data memory locations 24 31 This is the recommended setting for interrupt service routines since locations 0 7 are left intact The setting of P...

Page 115: ... routine after eight overflows and stop timer Count overflows in register 7 START MAIN DISTCNTI CLR A MOV T A MOV R7 A STRTT JTF COUNT JMP MAIN COUNT INC R7 MOV A R7 JB3 INT JMP MAIN DISABLE TIMER INTERRUPT CLEAR ACC TO ZEROS MOVE ZEROS TO TIMER MOVE ZEROS TO REG 7 START TIMER JUMP TO ROUTINE COUNT IF TF 1 AND CLEAR TIMER FLAG CLOSE LOOP INCREMENT REG 7 MOVE REG 7 CONTENTS TO ACC JUMP TO ROUTINE I...

Page 116: ...ter is incremented every 32 instruction cycles The prescaler which counts the 32 cycles is cleared but the timer register is not Example Initialize and start timer STARTT CLR A MOV T A EN TCNTI STRTT CLEAR ACC TO ZEROS MOVE ZEROS TO TIMER ENABLE TIMER INTERRUPT START TIMER SWAP A Swap Nibbles Within Accumulator 100 111 Bits 0 3 of the accumulator are swapped with bits 4 7 of the accumulator A4 7 X...

Page 117: ...mory location addressed by bits 0 5 of register r are exchanged Register r contents are unaffected A Rr r 0 1 Example Decrement contents of location 52 MOVE 52 DEC TO ADDRESS REG EXCHANGE CONTENTS OF ACC AND LOCATION 52 DECREMENT ACC CONTENTS EXCHANGE CONTENTS OF ACC AND LOCATION 52 AGAIN DEC52 MOV R0 52 XCH A R0 DEC A XCH A R0 XCHD A Rr Exchange Accumulator and Data Memory 4 Bit Data 00 11 000r T...

Page 118: ...REG 5 Example XRL A Rr Logical XOR Accumulator With Memory Mask 110 1 00 Or Data in the accumulator is EXCLUSIVE ORed with the mask contained in the data memory location addressed by register Y bits 0 5 A A XOR Rr r 0 1 Example XORDM MOV R1 20H XRL A R1 MOVE 20 HEX TO REG 1 XOR ACC CONTENTS WITH MASK IN LOCATION 32 XRL A data Logical XOR Accumulator With Immediate Mask 110 1 00 11 d7ded5d4 d3d2 d ...

Page 119: ...Chapter 5 APPLICATION EXAMPLES ...

Page 120: ... 8021 5 3 Stand Alone 8022 5 4 Multiple Interrupt Sources 5 5 Multiple Prioritized Interrupts 5 6 External Program Memory 5 7 Program Memory and I O Expansion 5 8 Data Memory and I O Expansion 5 9 A Three Chip System 5 10 I O Expansion Techniques 5 11 8049 Emulator Circuit 5 17 General Application Examples 5 19 5 2 Software Examples 5 22 ...

Page 121: ...pf r I XTAL1 20pf Z Z XTAL2 1 6 MHz 20pf r 470 1 K XTAL1 o XTAL2 5V XTAL1 L Nominal f TV COLOR BURST XTAL CAN BE USED CRYSTAL NOTE A STANDARD SERI ES RESONANT XTAL SUCH AS CTS KNIGHTS MP060 OR CRYSTEK CY6B WILL PROVIDE BETTER THAN 1 FREQUEN CY ACCURACY EACH C SHOULD BE APPROXIMATELY 20pF INCLUDING STRAY CAPACITANCE FOR MORE INFORMATION ON XTALS SEE INTEL APPLICATION NOTE AP 35 45 iH 5 2 mHz 120M H...

Page 122: ...3 24 PORT 2 INPUT AND 35 36 LOUTPUTJ 37 38 _ BUS PORT INPUT AND OUTPUT 8 NC NC All inputs and outputs except RESET X1 X2 standard TTL compatible P1 and P2 outputs drive 5V CMOS directly others require 10 to 50KH pullup for CMOS compatibility XTAL Series Resonant 1 to 6 MHz or Parallel Resonant for higher accuracy CTS Knights MP060 Crystek CY6B or equivalent or standard 3 58 MHz TV Color Burst XTAL...

Page 123: ...1 P12 18 19 20 DIODE OPTIONAL 8021 P13 P14 P15 P16 P17 22 23 24 25 INPUT 13 T1 P20 P21 P22 26 27 ALE PROG P23 2 PORT INPUT AND OUTPUT V PORT 1 INPUT AND OUTPUT INPUT AND OUTPUT 5V I r X x2 1 MEGfl x2 1K o TTL GATE XTAL 1 XTAL 2 LG CRYSTAL ALTERNATE FREQUENCY REFERENCE OPTIONS COMPONENT VALUES TO BE DETERMINED EXTERNAL THE STAND ALONE 8021 5 3 ...

Page 124: ... P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VTH POO P01 P02 P03 P04 P05 P06 P07 INPUT I AND outputJ INPUT I AND I outputJ r INPUT I AND OUTPUTJ 5V 1K Optional 1 MEG ft 6 3 6mHZ Xi O TTL GATE XTAL1 X2 XTAL2 CRYSTAL EXTERNAL ALTERNATE FREQUENCY REFERENCE OPTIONS COMPONENT VALUES TO BE DETERMINED THE STAND ALONE 8022 5 4 ...

Page 125: ... 3 DEVICE 4 OPEN COLLECTOR INVERTERS 5V 10K INT 8049 8048 8748 8035 8039 P10 ANY P11 UNDEDICATED PORT LINES P12 CAN BE USED All devices equal priority Processor polls Port 1 to determine interrupting device MULTIPLE INTERRUPT SOURCES 5 5 ...

Page 126: ...APPLICATION EXAMPLES INTERRUPT INPUTS Processor polls Port 1 to determine interrupting device Processor sets priority level by writing 4 bits to 8214 MULTIPLE INTERRUPTS WITH PRIORITY LEVELS 5 6 ...

Page 127: ... P23 P24 P25 P26 P27 DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 EA 5V FOR 8035 8039 Vcc GND 8212 LATCH Dh DOi Dl 2 D02 Dl 3 DO3 DU DO4 Dl 5 D05 Dl 6 D06 DI7 DO7 Dl 8 D08 CLR DS2 MD DS 13 or 19 21 Vdd Vbb Vss 8708 1Kx 8 EPROM 8212 serves as address latch Address is valid while ALE is high and is latched when ALE goes low EXTERNAL PROGRAM MEMORY 5 7 ...

Page 128: ... Vss ce A8 A9 A10 ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 fOR lOW RD ALE CE RESET 8355 8755A 2Kx8 ROM JI I 3 I 6 NC NC PAO PA1 PA2 PA3 PA4 PA5 PA6 PA7 PBO PB1 PB2 PB3 PB4 PB5 PB6 PB7 I O External I O ports are addressed as data memory PA 00 PB 01 If the 8048s internal Program Memory is used this configuration will result in the upper 1K of external memory being addressed before the lower 1K Inverting A10 ...

Page 129: ... BY SYSTEM RESET OR PORT LINE OF 8048 GND 20 vCc Vss ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 IO M RD WR 8155 256 x 8 RAM RESET TIMER OUT TIMER IN TIMER PAO PA1 PA2 PA3 PA4 PA5 PA6 PA7 PCO PC1 PC2 PC3 PC4 PC5 PBO PB1 PB2 PB3 PB4 PB5 PB6 PB7 21 22 23 24 25 26 27 28 37 38 39 J 2 5 29 30 31 32 33 34 35 36 I O Both I O and RAM are addressed as data memory Writing a bit to P27 determines whether RAM or I O is t...

Page 130: ...R PORT LINE OF 8048 5V 5V GND GND 40 5 20 1 A8 A9 A10 ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 IOR IOW RD ALE CE RESET Vcc vDd Vss ce 8355 8755A 2Kx8 ROM 7 3 6 r NC NC GND 20 vCc Vss ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 8156 256 x 8 RAM RESET TIMER OUT PAO PA1 PA2 PA3 PA4 PA5 PA6 PA7 PBO PB1 PB2 PB3 PB4 PB5 PB6 PB7 PAO PA1 PA2 PA3 PA4 PA5 PA6 PA7 PCO PC1 PC2 PC3 PC4 PC5 PBO PB1 PB2 PB3 PB4 PB5 PB6 PB7 I O This ...

Page 131: ...se techniques can be used whenever the combination memory IO expanders illustrated on the preceeding pages are not required 40 26 20 INPUT 39 10 T1 6 _ INT VCC VDD Vss XTAL 1 8049 8048 8748 8035 8039 ALE PSEN PROG WR RD P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vcc P40 P41 P42 P43 P50 P51 8243 I O P52 P53 EXPANDER P60 P20 P61 P21 P62 P22 P63 P2...

Page 132: ... 8022 ALE PROG POO P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 Vcc 8243 I O EXPANDER P20 P21 P22 P23 PROG CS P40 P41 P42 P43 P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 PIN NUMBERS ARE DIFFERENT FOR 8022 ADDING AN I O EXPANDER TO THE 8021 8022 5 12 ...

Page 133: ... DB1 DB2 DB3 DB4 DB5 DB6 DB7 12 _ 13 14 15 16 17 18 19 PIN NUMBERS ARE DIFFERENT FOR 8021 8022 I I I Vcc 8243 I O EXPANDER P20 P21 P22 P23 PROG CS 5V 124 GND 12 Vcc 8243 I O EXPANDER P20 P21 P22 P23 PROG CS I I I I I I I I I l I I I I P40 P41 P42 P43 P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 P40 P41 P42 P43 P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 I O ADDING MULTIPLE I O EXPANDERS 5 1...

Page 134: ...ction of the output loading and the characteristics of the input signals ADDING 8 INPUT LINES Vcc Vdd Vss XTAL 1 8049 8048 8748 P22 P23 P24 P25 P26 P27 DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 ALE PSEN PROG WR RD S 74LS259 16 Individual bits of the 74LS259 eight bit addressable latch can be set or reset using the OUTL instruction During the OUTL operation bit zero of the accumulator is written into the bit...

Page 135: ...NG 16 INPUT LINES V CfJD 40 26 20 Vcc Vdd Vss pm 27 XTAL1 ph pi 28 29 3 XTAL 2 P13 P14 PI S 30 31 32 4 RESET P16 P17 33 34 P 0 21 EA 8049 P21 22 23 8048 P23 24 SS TO 8748 P24 P25 P26 P27 DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 35 3 5 37 38 12 S 14 6D 5D 4D 3D 2D 1D 6Q 5Q 40 3Q 2Q 10 39 13 j 13 T1 14 j 11 74LS174 16 15 j 6 6 INT 16 j 4 17 r 3 CLK 18 19 9 ALE PSEN PROG WR RD 11 9 25 10 8 The latch can be lo...

Page 136: ...the 74LS164 eight bit shift register will be used to scan a display and or keyboard In this case an ANLD P7 A with A 0FFH can be used to load the initial 1 and an ANLD P6 A with A 0FEH can be used to move it down the shift register QA QB QC QD QE QF QG QH 74 LSI 64 14 PIN NUMBERS ARE DIFFERENT FOR 8021 8022 ADDING OUTPUT FOR KEYBOARD DISPLAY SCANNING 5 16 ...

Page 137: ...APPLICATION EXAMPLES NOTE P 23 IS SHOWN HERE CONNECTED FOR OUTPUT P22 IS CONNECTED FOR INPUT 8049 EMULATOR CIRCUIT 5 17 ...

Page 138: ...tput and strobed input If DB79DB of the 8049 are to be used solely for input data J2 and J3 may NOTE FOR EMULATION AT 11 MHZ 1 Substitute a 2716 1 2 Delete 74LS03 package leave lines open Elimination of 74LS03 precludes use of P20 P23 as inputs be changed from what is shown in the Figure so that DB7 DB act as high impedance inputs and the 8216s are enabled only when the read operation is performed...

Page 139: ...DRUM PRINTER PU HAN 1000 PULSE GAL r MP DLE F RD 8048 PROG PORT 2 PORT 1 3 8251 USART CS CD CS 8243 _ CS 8243 _ CS 8243 A N N 1 _ 8 4 4 4 WR A i 4 TO CENTRAL TERMINAL 1 4 4 A 4 a 1 4 F LAMP CK 4 N 3 S anned SCANNED Xj FUEL 1 4 1 i 2 3 4 9 9 9 9 9 9 9 9 9 VALVES FUEL TYPE ROTARY PRICE PRICE VOLUME SCAN LI NES MCS 48 GAS PUMP 5 19 ...

Page 140: ...CE 7 IZ TO OPTIONAL COMMUNICATIONS INTERFACE READER STORE AND FORWARD 8279 KEYBOARD DISPLAY SCAN LINES iz CASH REGISTER KEYBOARD NUMERIC DEPT ITEM TAX ETC iz FRONT AND REAR DUAL DISPLAY SEVEN SEGMENT UK I INDICATOR LAMP MATRIX FOR ILLUMINATED KEY TOPS DRUM PRINTER MAY BE USED DRUM PRINTER REQUIRES MORE OUTPUTS WHICH CAN BE OBTAINED FROM AN EXPANDER DEVICE LOW COST POINT OF SALE TERMINAL 5 20 ...

Page 141: ...CELERATE ENGINE CRANKING Wv 1 7 C VEHICLE TYPE IDENTIFICATION POWER TRAIN TYPE IDENTIFICATION SIMPLE FEEDBACK CARBURETOR CONTROLLER POWER SUPPLY MAGNETRON TRIAC DOOR INTERLOCK 60Hz TIMING REFERENCE FRONT PANEL 4x4 KEYBOARD STATUS INDICATORS N UU UU V UU UU z Z MICROWAVE OVEN CONTROLLER 5 21 ...

Page 142: ...OUBLE SUBTRACT DMIN DEC CPL ADD CPL INC XCH CPL ADDC CPL XCH RET DOUBLE LOAD DLD DEC MOV INC XCH MOV XCH RET DOUBLE STORE DST DEC MOV INC XCH MOV XCH RET RXO A A RX0 A RXO A AEX A A RX0 A A AEX RXO A RX0 RXO A AEX A RX0 A AEX RXO RX0 A RXO A AEX RX0 A A AEX GET LOW BYTE AND ADD TO A GET HI BYTE AND ADD TO AEX RETURN GET LOW BYTE AND SUB FROM A GET HI BYTE AND SUB FROM AEX RETURN GET LOW BYTE AND P...

Page 143: ...assumes a one byte multiplier and a one byte multiplicand The product therefore is two bytes long The algorithm follows these steps 1 The registers are arranged as follows ACC R1 Multiplier R2 Multiplicand R3 Loop Counter 8 The Accumulator and register R1 are treated as a register pair when they are shifted right see Step 2 2 The Accumulator and R1 are shifted right one place thus the LSB of the m...

Page 144: ... HANDLING This interrupt routine assumes single level interrupt The purpose is to store the status of the machine at the time the interrupt occurs by storing contents of all registers accumu lator and the status word At the end of the interrupt the state of the machine is restored and interrupts are enabled again INTRPT SEL MOV i i MOV MOV RETR RB1 SAVE WORKING REGISTERS R0 A R0 IN ALTERNATE REGIS...

Page 145: ...the Larger to a Third Port 1ST OUTPUT 2ND OUTPUT 1ST GD PROCESS CLR IN MOV IN MOV CPL INC ADD JZ JNC MOV OUTL JMP SECOND MOV OUTL JMP EQUL CPL JMP FO A P1 RO A A P2 R1 A A A A RO EQUL SECOND A R0 BUS A DONE A R1 BUS A DONE FO DONE CLEAR FO BIT INITIALIZE READ FIRST INPUT STORE IN RO READ SECOND INPUT STORE IN R1 SUBTRACT SECOND FROM FIRST 2 s COMPLEMENT AND ADD BRANCH IF THEY ARE EQUAL IF NEGATIVE...

Page 146: ...IS UTILITY PROVIDES AH 8 BY 8 UNSIGHED MULTIPLY AT ENTRY A LOWER EIGHT BITS OF DESTINATION OPERAHD XA DON T CARE Rl POIHTER TO SOURCE OPERAND MULTIPLIER IN INTERNAL MEMEORY AT EXIT A LOWER EIGHT BITS OF RESULT XA UPPER EIGHT BITS OF RESULT C SET IF OVERFLOW ELSE CLEARED 1 HPY8X8 1 MULTIPLICAND 1 5 8 1 B 1 C0UNT 8 1 REPEAT 2 IF MULTIPLICAND B 8 THEN BEGIN 3 MULTIPLICANDi MULTIPLICAND 2 2 ELSE 3 MUL...

Page 147: ...153 i COUNT 8 1 154 MOV COUNT 8 1 155 l REPEAT 1 156 MPV8LP 1 157 2 IF MULTIPLICANDt B J B THEN BEGIN 1 158 JBB MPY8A 1 159 3 MULTIPLICAND MULTIPLICANDS 1 16B XCH A XA 1 161 CLR C 1 162 RRC A 1 163 XCH A XA I 164 RRC A 1 165 DJNZ COUNT MPY8LP 1 166 RET 1 167 2 ELSE 1 168 MPY8A 1 169 3 MULTIPLICANDt 15 8 MULTIPLI Is 17B XCH A XA Is 171 ADD A BR1 la 172 RRC A Is 173 XCH A XA Is 174 RRC A Is 175 DJNZ...

Page 148: ... DIV16 I THIS UTILITY PROVIDES AN 16 BY 8 UNSIGNED DIVIDE AT ENTRY A LOWER EIGHT BITS OF DESTINATION OPERAND XA UPPER EIGHT BITS OF DIVIDEND Rl POINTER TO DIVISOR IN INTERNAL MEMORY AT EXIT A LOWER EIGHT BITS OF RESULT XA REMAINDER C SET IF OVERFLOW ELSE CLEARED 1 DIV16 DI V16 XCH A XA l COUNT 8 MOV COUNT 8 1 DIVIDEND 15 8I DIVIDEND 15 8 DIVISOR CPL A ADD A 8R1 CPL A il IF BORROW 0 THEN IT FITS J ...

Page 149: ...39 CPL A IF BORROUM THEN BB66 E66B 24B 241 JNC DIVIC RESTORE DIVIDEND BB68 61 242 ADD A R1 BB69 B46C 243 244 245 246 OIVIC JflP DIVID ELSE QUOTIENTCB l BB6B 1A 247 248 249 INC XA ENDIF COUNT COUNT l 2SB UNTIL COUNT B BB6C EB57 251 DIVIO DJN2 COUNT DIVILP 252 CLEAR OVERFLOW FLAG BB6E 97 253 CLR C 254 ENDIF 255 ENDDIVIDE BB6F 2A 2S6 DIVIB XCH A XA 8B7S 83 257 RET 5 29 ...

Page 150: ......

Page 151: ...Chapter 6 MCS 48 COMPONENT SPECIFICATIONS ...

Page 152: ...puters 6 10 M8048 M8748 M8035 Military Temperature Microcomputers 6 19 8049 8039 8039 6 Microcomputers 6 28 8021 Microcomputer 6 33 8022 Microcomputer 6 36 8243 I O Expander 6 42 I8243 Industrial Temperature 8243 6 48 8355 ROM and I O Expander 6 54 8755 EPROM and I O Expander 6 59 8155 8156 RAM and I O Expander 6 67 8185 8185 2 1024 X 8 Bit Static RAM FOR MCS 85 6 81 ...

Page 153: ...ws for very fast turnaround for initial code verification and evaluation units To reduce develop ment problems to a minimum and provide maximum flexibility three interchangeable pin compatible versions of this single component microcomputer exist the 8748 with user programmable and erasable EPROM program memory for prototype and preproduction systems the 8048 with factory programmed mask ROM progr...

Page 154: ...able using the JT1 and JNT1 instructions Can be des ignated the timer counter input using the STRT CNT instruction 6 Interrupt input Initiates an inter rupt if interrupt is enabled Inter rupt is disabled after a reset Also testable with conditional jump instruction Active low Designation Pin Function RD RESET WR ALE PSEN SS EA XTAL1 XTAL2 8 Output strobe activated during a BUS read Can be used to ...

Page 155: ... carry 1 2 2 JNCaddr Jump on carry 2 2 J 2 addr Jump on A zero 2 2 JNZaddr Jump on A not zero 2 2 u c IS JTO addr Jump on TO 1 2 2 JNTO addr Jump on TO 2 2 GO JT1 addr Jump on T1 1 2 2 JNT1 addr Jump on T1 2 2 JFOaddr Jump on FO 1 2 2 JF1 addr Jump on F1 1 2 2 JTF addr Jump on timer flag 2 2 JNI addr Jump on INT 2 2 JBb addr Jump on accumulator bit 2 2 c CALL addr Jump to subroutine 2 2 3 o RET Re...

Page 156: ... All Except RESET X1 X2 5 8 V V L1 Input Low Voltage RESET X1 X2 5 6 V V H Input High Voltage 2 0 Vcc V All Except XTAL1 XTAL 2 RESET V H1 Input High Voltage X1 X2 RESET 3 8 Vcc V Vol Output Low Voltage BUS 45 V VOL 2 0 mA Vou Output Low Voltage RD WR PSEN ALE 45 V l 0L 1 8 mA V0L2 Output Low Voltage PROG 45 V l OL 1 0 mA VOL3 Output Low Voltage All Other Outputs 45 V l 0L 1 6 mA VOH Output High V...

Page 157: ...8 Unit Conditions Note 1 Min Max Min Max t _L ALE Pulse Width 400 600 ns tAL Address Setup to ALE 120 150 ns tLA Address Hold from ALE 80 80 ns t CC Control Pulse Width PSEN RD WR 700 1500 ns tow Data Setup before WR 500 640 ns WD Data Hold After WR 120 120 ns CL 20pF tCY Cycle Time 2 5 15 0 4 17 15 0 Ms 6MHzXTAL 2 5 3 6 MHz XTAL for 8 DR Data Hold 200 200 ns l RD PSEN RD to Data In 500 750 ns t A...

Page 158: ...alling Edge of PROG 100 ns tPR PROG to Time P2 Input Must Be Valid 810 ns tPF Input Data Hold Time 150 ns tDP Output Data Setup Time 250 ns tPD Output Data Hold Time 65 ns tpp PROG Pulse Width 1200 ns tPL Port 2 I O Data Setup 350 ns tLP Port 2 I O Data Hold 150 ns PORT 2 TIMING y EXPANDER PORT DC EXPANDER PORT IX v V X PORT 2n 3 DATA X PORT 2 a i DATA PORT CONTROL PORT CONTROL X OUTPUT DATA c X I...

Page 159: ...escrip tion of their functions Pin Function XTAL1 Clock Input 1 to6MHz Reset Initialization and Address Latching TestO Selection of Program or Verify Mode EA Activation of Program Verify Modes BUS Address and Data Input Data Output During Verify P20 1 Address Input Vdd Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a missocketed 8748 will result in severe damage to...

Page 160: ...tch Address 4tcy tr tf Vdd and PROG Rise and Fall Times 0 5 2 0 MS tCV CPU Operation Cycle Time 5 0 MS tRE RESET Setup Time Before EA r 4tcy Note If Test is high tDO can be triggered by RESET t DC SPECIFICATION FOR PROGRAMMING TA 25 C 5 C Vcc 5V 5 Vdd 25V 1V Symbol Parameter Min Max Unit Test Conditions Vdoh Vdd Program Voltage High Level 24 0 26 0 V Vddl Vdd Voltage Low Level 4 75 5 25 V Vph PROG...

Page 161: ...8 PROG MUST ALWAYS FLOAT 2 X1 AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5jisec trjY THIS IS ACCEPTABLE FOR 8 PARTS AS WELL AS STANDARD PARTS NEXT ADDRESS VALID The 8748 EPROM can be programmed by either of two Note See the ROM PROM section for 8048 ROM ordering procedures Intel DTOduCtS To min i m ze turnaround time on the first 25 pieces 8648 may be 1 PROMPT 48 Microcomputer Design Aid or 2 Universa...

Page 162: ...itution of 8648 s for 8048 s allows for very fast turnaround for initial code verification and evaluation units To reduce development problems to a minimum and provide maximum flexibility three interchangeable pin compati ble versions of this single component microcomputer exist the 8748 with user programmable and erasable EPROM program memory for prototype and preproduction systems the 8048 with ...

Page 163: ...g T1 39 Input pin testable using the JT1 and JNT1 instructions Can be des ignated the timer counter input using the STRT CNT instruction INT 6 Interrupt input Initiates an inter rupt if interrupt is enabled Inter rupt is disabled after a reset Also testable with conditional jump instruction Active low RD RESET WR ALE PSEN SS EA XTAL1 XTAL2 8 Output strobe activated during a BUS read Can be used to...

Page 164: ... 2 JNZaddr Jump on A not zero 2 2 JTO addr Jump on TO 1 2 2 JNTO addr Jump on TO 2 2 JT1 addr Jump on T1 1 2 2 JNT1 addr Jump on T1 2 2 JFOaddr Jump on FO 1 2 2 JF1 addr Jump on F1 1 2 2 JTF addr Jump on timer flag 2 2 JNI addr Jump on INT 2 2 JBbaddr Jump on accumulator bit 2 2 c CALL addr Jump to subroutine 2 2 3 o RET Return 1 2 O 3 CO RETR Return and restore status 1 2 CLR C Clear carry 1 CPL ...

Page 165: ...r Input Low Voltage All Except RESET XTAL1 XTAL2 Input Low Voltage RESET X1 X2 Input High Voltage All Except XTAL1 XTAL2 RESET Input High Voltage XTAL1 XTAL2 RESET Output Low Voltage BUS RD WR PSEN ALE Output Low Voltage P10 P17 P20 P27 Output Low Voltage All Other Outputs Output High Voltage BUS Output High Voltage RD WR ALE PSEN Output High Voltage All Other Outputs Input Leakage Current T1 INT ...

Page 166: ...48 8035L 8748 8035 Unit Conditions Note 1 Min Max Min Max tLL ALE Pulse Width 200 300 ns tAL Address Setup to ALE 120 120 ns tLA Address Hold from ALE 80 80 ns l CC Control Pulse Width PSEN RD WR 400 600 ns DW Data Setup Before WR 420 600 ns t A D Data Hold After WR 80 120 ns CL 20pF CY Cycle Time 2 5 15 0 4 17 15 0 MS 3 6 MHz XTAL 8748 8035 DR Data Hold 200 200 ns RD PSEN RD to Data In 400 600 ns...

Page 167: ...of PROG 65 ns tpR PROG to Time P2 Input Must Be Valid 860 ns tpF Input Data Hold Time 160 ns DP Output Data Setup Time 230 ns tpD Output Data Hold Time 25 ns tpp PROG Pulse Width 920 ns tpL Port 2 I O Data Setup 300 ns LP Port 2 I O Data Hold 120 ns PORT 2 TIMING EXPANDER PORT DC EXPANDER PORT DC r X K Y DP PORT 2 3 DATA Ifl PORT CONTROL OUTPUT DATA V PORT 2 _ 3 DATA M PORT 2 3 DATA rW PORT CONTRO...

Page 168: ... their functions Pin Function XTAL1 Clock Input 1 to 6 MHz RESET Initialization and Address Latching TEST Selection of Program or Verify Mode EA Activation of Program Verify Modes BUS Address and Data Input Data Output during Verify P20 1 Address Input VDd Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a mis socketed 8748 will result in severe damage to the part An...

Page 169: ...ch Address 4tcy tr tf Vdd and PROG Rise and Fall Times 0 5 2 0 MS tCY CPU Operation Cycle Time 5 0 MS tRE RESET Setup Time Before EA I 4tcy Note If Test is high too can be triqqered bv RESET I DC SPECIFICATION FOR PROGRAMMING Ta 25 C 5 C Vcc 5V 5 Vdd 25V 1V Symbol Parameter Min Max Unit Test Conditions Vdoh Vdd Program Voltage High Level 24 0 26 0 V Vddl Vdd Voltage Low Level 4 75 5 25 V VPH PROG ...

Page 170: ...23V OR IF TO 5V FOR THE 8748 FOR THE 8048 PROG MUST ALWAYS FLOAT 2 Xi AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5psec tCY THIS IS ACCEPTABLE FOR 8 PARTS AS WELL AS STANDARD PARTS NEXT ADDRESS XNEXT DATA OUT VALID r NEXT ADDRESS VALID The 8748 EPROM can be programmed by either Of two Note See the ROM PROM section for 8048 ROM ordering procedures Intel products To minimize turnaround time on the first ...

Page 171: ...terchangeable pin compatible versions of this single component microcomputer exist the M8748 with user programmable and erasable EPROM program memory for prototype and preproduction systems the M8048 with factory programmed mask ROM program memory for low cost high volume production and the M8035 without program memory for use with external program memories This microprocessor is designed to be an...

Page 172: ...g and a descrip tion of their functions Pin Function XTAL1 Clock Input 1 to6MHz Reset Initialization and Address Latching TestO Selection of Program or Verify Mode EA Activation of Program Verify Modes BUS Address and Data Input Data Output During Verify P20 1 Address Input VDD Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a missocketed 8748 will result in severe ...

Page 173: ...atch Address 4icy tr tf Vdd and PROG Rise and Fall Times 0 5 2 0 MS tCY CPU Operation Cycle Time 5 0 MS tRE RESET Setup Time Before EA 4tcy Note If Test is high tDO can be triggered by RESET t DC SPECIFICATION FOR PROGRAMMING Ta 25 C 5 C Vcc 5V 5 Vdd 25V 1V Symbol Parameter Min Max Unit Test Conditions Vdoh Vdd Program Voltage High Level 24 0 26 0 V Vddl Vdd Voltage Low Level 4 75 5 25 V Vph PROG ...

Page 174: ...ID A v V X ADDRESS 8 9 VALID X NEXT ADDRESS X NEXT DATA OUT VALID f NEXT ADDRESS VALID NOTES 1 PROG MUST FLOAT IF EA IS LOW i e 23V OR IF TO 5V FOR THE 8748 FOR THE 8048 PROG MUST ALWAYS FLOAT 2 Xt AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5 isectcY THIS IS ACCEPTABLE FOR ALL PARTS The 8748 EPROM can be programmed by either of two Intel products 1 PROMPT 48 Microcomputer Design Aid or 2 Universal PRO...

Page 175: ...ddr Jump on carry 2 2 JZaddr Jump on A zero 2 2 JNZ addr Jump on A not zero 2 2 u c JTO addr Jump on T0 1 2 2 m JNTO addr Jump on T0 2 2 JT1 addr Jump on T1 1 2 2 JNT1 addr Jump on T1 0 2 2 JFO addr Jump on F0 1 2 2 JF1 addr Jump on F1 1 2 2 JTF addr Jump on timer flag 2 2 JNI addr Jump on INT 2 2 JBb addr Jump on accumulator bit 2 2 c CALL Jump to subroutine 2 f ji o RET Return 1 2 a 3 A RETR Ret...

Page 176: ...le using the JT1 and JNT1 instructions Can be designated the timer counter in put using the STRT CNT in struction Designation Pin Function INT RD RESET WR ALE PSEN SS EA XTAL1 XTAL2 6 Interrupt input Initiates an inter rupt if interrupt is enabled Inter rupt is disabled after a reset Also testable with conditional jump instruction Active low 8 Output strobe activated during a BUS read Can be used ...

Page 177: ...ort Control Hold After Falling 65 ns Edge of PROG tPR PROG to Time P2 Input Must Be Valid 860 ns tPF Input Data Hold Time 160 ns tDP Output Data Setup Time 230 ns tPD Output Data Hold Time 25 ns tpp PROG Pulse Width 920 ns tPL Port 2 I O Data Setup 300 ns tLP Port 2 I O Data Hold 120 ns PORT 2 TIMING j EXPANDER PORT DC EXPANDER PORT DC y PORT 2 3 DATA X PORT 2o 3 DATA X PORT CONTROL F DRT CONTROL ...

Page 178: ...ameter 8048 8035L 8748 8035 Unit Conditions Note 1 Min Max Min Max tLL ALE Pulse Width 200 300 ns tAL Address Setup to ALE 120 120 ns tLA Address Hold from ALE 80 80 ns tec Control Pulse Width PSEN RD WR 400 600 ns tow Data Setup before WR 420 600 ns twD Data Hold After WR 80 120 ns CL 20pF tCY Cycle Time 2 5 15 0 4 17 15 0 Ms 3 6 MHz XTAL 8748 8035 tDR Data Hold 200 200 ns tRD PSEN RDto Data In 4...

Page 179: ...s 0V Symbol Parameter Limits Unit Test Conditions Min Typ Max V L Input Low Voltage All Except RESET X1 X2 5 7 V V L 1 Input Low Voltage RESET X1 X2 5 5 V V H Input High Voltage 2 3 Vcc V All Except XTAL1 XTAL 2 RESET V H1 Input High Voltage RESET X1 X2 3 8 Vcc V Vol Output Low Voltage BUS RD WR PSEN ALE 45 V Iol 1 2mA Von Output Low Voltage All Other Outputs 45 V Iol 0 8mA VoH Output High Voltage...

Page 180: ...wo interchangeable pin compatible versions of this single component microcomputer exist the 8049 with factory programmed mask ROM program memory for low cost high volume production and the 8039 without program memory for use with external program memories in prototype and preproduction systems This microprocessor is designed to be an efficient controller as well as an arithmetic processor The 8049...

Page 181: ...he timer counter input using the STRT CNT instruction Interrupt input Initiates an inter rupt if interrupt is enabled Inter rupt is disabled after a reset Also testable with conditional jump instruction Active low RESET WR ALE PSEN SS EA XTAL1 XTAL2 8 Output strobe activated during a BUS read Can be used to enable data onto the BUS from an external device Used as a Read Strobe to External Data Mem...

Page 182: ... Jump on TO 1 2 2 re JNTO addr Jump on TO 2 2 00 JT1 addr Jump on T1 1 2 2 JNT1 addr Jump on T1 2 2 JFOaddr Jump on FO 1 2 2 JF1 addr Jump on F1 1 2 2 JTF addr Jump on timer flag 2 2 JNI addr Jump on INT 2 2 JBb addr Jump on Accumulator Bit 2 2 Description Bytes Cycles c CALL Jump to subroutine 2 2 3 O RET Return 1 2 0 3 CO RETR Return and restore status 1 2 CLR C Clear Carry 1 1 CPL C Complement ...

Page 183: ...ther Outputs Except PROG 0 45 V Iql 1 6mA VOL2 Output Low Voltage PROG 0 45 V Iql 1 0mA V H Output High Voltage BUS RD WR PSEN ALE 2 4 V Iqh 100JIA VOH1 Output High Voltage All Other Outputs 2 4 V Iqh 50 iA IlL Input Leakage Current T1 fNT 10 MA Vss V N VCc lOL Output Leakage Current Bus TO High Impedance State 10 A VSS 0 45 V N Vcc DD Power Down Supply Current 25 50 mA TA 25 C dd cc Total Supply ...

Page 184: ...RAM MEMORY ALE PSEN l LL BUS FLOATING ADDRESS C tec L V FLOATING V V FLOATING V INSTRUCTION READ FROM EXTERNAL DATA MEMORY ALE RD J L FLOATING BUS FLOATING AdDRESsV DATA FLOATING WRITE TO EXTERNAL DATA MEMORY ALE WR BUS FLOATINGyADDRESSyFLOATINGX DATA FLOATING 6 32 ...

Page 185: ...is designed to be an efficient controller as well as an arithmetic processor The 8021 has bit handling capability as well as facilities for both binary and BCD arithmetic Efficient use of program memory results from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in length To minimize the development problems and maximize flexibility an 8021 syst...

Page 186: ...mbol Min Typ Max Test Conditions V L Input Low Voltage 0 5 0 8 V V H Input High Voltage All except XTAL 1 RESET 2 0 Vcc V VCC 5 0V 10 V H1 Input High Voltage All except XTAL1 RESET 3 0 Vcc V VCc 5 5V 1V Vol Output Low Voltage 0 45 V Iol 1 6 mA Volt Output Low Voltage P10 P1 1 2 5 V Iol 7 mA VOH Output High Voltage All unless Open Drain 2 4 V lOH 40 mA Ilo Output Leakage Current Open Drain Option P...

Page 187: ...a Exclusive Or immediate 2 to A 2 D3 INC A Increment A 1 1 17 DEC A Decrement A 1 1 07 CLR A Clear A 1 1 27 CPL A Complement A 1 1 37 DA A Decimal adjust A 1 1 57 SWAP A Swap nibbles of A 1 1 47 RL A Rotate A left 1 1 E7 RLC A Rotate A left through 1 carry 1 F7 RR A Rotate A right 1 1 77 RRC A Rotate A right through 1 carry 1 67 IN A P p Input port to A 1 2 08 09 0A 3 OUTL P p A Output A to port 1...

Page 188: ...ces external and timer interrupts and zero cross detection capabili ty In addition it contains the 8 bit interval timer event counter on board oscillator and clock circuitry single 5V power supply requirement and easily expandable I O structure common to all members of the MCS 48 family The 8022 is designed to be an efficient controller as well as an arithmetic processor It has bit handling capabi...

Page 189: ...ero cross detection input to allow zero crossover sensing of slowly moving AC inputs Op tional pull up resistor may be added via ROM mask selection RESET 24 AVSs 7 AVcc 3 SUBST 21 Varef ANO AN1 6 5 ALE 18 XTAL 1 22 XTAL 2 23 Input used to initialize the proc essor by clearing status flip flops and setting the program counter to zero A D converter GND Potential Also establishes the lower limit of t...

Page 190: ... Input Low Voltage Port 0 0 5 Vjh 0 1 V V H High Voltage All except XTAL 1 RESET 2 0 Vcc V VCc 5 0V 10 Vjh Floating V H1 Input High Voltage All except XTAL 1 RESET 3 0 Vcc V VCc 5 5V 1V Vjh Floating V H2 Input High Voltage Port 0 Vjh 0 1 Vcc V V H3 Input High Voltage RESET XTAL 1 3 0 Vcc V VTH Port Threshold Reference Voltage 4Vcc V Vol Output Low Voltage 0 45 V Iol 16 mA VOL1 Output Low Voltage P...

Page 191: ...t Must Be Valid 1 0 MS DP Output Data Setup Time 7 0 MS tPD Output Data Hold Time 8 3 MS tPF Input Data Hold Time 150 MS tpp PROG Pulse Width 8 3 MS tPRL ALE to Time P2 Input Must Be Valid 3 6 MS tPL Output Data Setup Time 0 8 MS t _P Output Data Hold Time 1 6 MS PFL Input Data Hold Time MS LL ALE Pulse Width 3 9 23 0 MS tcY 8 38 ms for min PORT 2 TIMING EXPANDER PORT OUTPUT EXPANDER PORT INPUT DC...

Page 192: ...ld After Falling Edge of ALE Osh 0 10 CY Note 2 Input Capacitance ANO AN1 1 PF Conversion Time 4 4 CY Z j IDEAL TRANSITION SWITCH POINT ACCURACY I itt I 2 3 253 254 56 256 256 256 ANALOG INPUT OF FUU SCALE ANALOG INPUT TIMING X X r NOTES 1 The Switch Point Accuracy measures the variation of the actual switch points from the transitions of an ideal A D converter over the full conversion range 2 The...

Page 193: ...2 2 E6 JZ addr Jump on A zero 2 2 C6 JNZ addr Jump on A not zero 2 2 96 Description Hexadecimal Bytes Cycle Opcode JTO Jump on T0 1 2 2 36 JNTO Jump on T0 0 2 2 26 JT1 addr Jump on T1 1 2 2 56 JNT1 addr Jump on T1 0 2 2 46 JTF addr Jump on timer flag 2 2 16 s CALL addr Jump to subroutine S CLRC i CPLC Clear carry Complement carry MOV A R r MOV A R MOV A data MOV Rr A MOV R A MOV Rr data e o MOV R ...

Page 194: ...omputers The 4 bit interface requires that only 4 I O lines of the 8048 be used for I O expansion and also allows multiple 8243s to be added to the same bus The I O ports of the 8243 serve as a direct extension of the resident I O facilities of the MCS 48 microcomputers and are accessed by their own MOV ANL and ORL instructions PIN CONFIGURATION BLOCK DIAGRAM P50C y 24 3Vcc P40C 2 23 DP51 P41C 3 2...

Page 195: ... 8035 Power On Initialization Initial application of power to the device forces input output ports 4 5 6 and 7 to the tri state and port 2 to the input mode The PROG pin may be either high or low when power is applied The first high to low transition of PROG causes device to exit power on mode The power on sequence is initiated if Vcc drops below 1V P21 P20 Address Code P23 P22 In struction Code 1...

Page 196: ...4 7 0 45 V Iql 5 mA VOL2 Output Low Voltage Port 7 1 V Iql 20 mA VOH1 Output High Voltage Ports 4 7 2 4 V l 0H 240juA l L1 Input Leakage Ports 4 7 10 20 uA Vin VCc to 0V lL2 Input Leakage Port 2 CS PROG 10 10 MA Vin VCc to 0V VOL3 Output Low Voltage Port 2 45 V In 6 mA cc Vcc Supply Current 10 20 mA VOH2 Output Voltage Port 2 2 4 l 0H 100juA OL Sum of all IO _ from 16 Outputs 80 mA 5 mA Each Pin S...

Page 197: ...8243 WAVEFORMS te v v v V X INSTRUCTION V FLOAT V DATA X A A A A j XX OUTPUT XX A A PREVIOUS OUTPUT VALID IP X INPUT VALID XOUTPUT VALID X y 6 45 ...

Page 198: ...5 TTL loads 1 6 mA assuming remaining pins are unloaded I l 5 x 1 6 mA 8 mA l OL 60 mA from curve pins 60 mA r 8 mA pin 7 5 7 In this case 7 lines can sink 8 mA for a total of 56 mA This leaves 4 mA sink current capa bility which can be divided in any way among the remaining 8 I O lines of the 8243 Example This example shows how the use of the 20 mA sink capability of Port 7 affects the sink ing c...

Page 199: ...243 EXPANDER INTERFACE CO TEST INPUTS 1 8243 OUTPUT EXPANDER TIMING CZK ADDRESS 4 BITS DATA 4BITS 00 READ 01 WRITE 10 OR 11 AND PROG P203 7T CO co CO ICO PROG P20 3 CO CO CO KO USING MULTIPLE 8243s 6 47 ...

Page 200: ...rface to the MCS 48 microcomputers The 4 bit interface requires that only 4 I O lines of the 8048 be used for I O expansion and also allows multiple 8243 s to be added to the same bus The I O ports of the 8243 serve as a direct extension of the resident I O facilities of the MCS 48 microcomputers and are accessed by their own MOV ANL and ORL instructions PIN CONFIGURATION BLOCK DIAGRAM P50 C 1 v 2...

Page 201: ...048 8748 8035 Power On Initialization Initial application of power to the device forces input output ports 4 5 6 and 7 to the tri state and port 2 to the input mode The PROG pin may be either high or low when power is applied The first high to low transition of PROG causes device to exit power on mode The power on sequence is initiated if V c drops below 1V P21 P20 Address Code P23 P22 Instruction...

Page 202: ...ts 4 7 0 45 V Iol 5 mA VOL2 Output Low Voltage Port 7 1 V l L 20 mA VOH1 Output High Voltage Ports 4 7 2 4 V l 0H 240juA l L1 Input Leakage Ports 4 7 10 20 iA Vin Vcc to0V IL2 Input Leakage Port 2 CS PROG 10 10 ma Vin VCC to 0V VOL3 Output Low Voltage Port 2 45 V l _ 6 mA cc Vcc Supply Current 10 20 mA VOH2 Output Voltage Port 2 2 4 l 0H 100 iA OL Sum of all IO _ from 16 Outputs 80 mA 5 mA Each Pi...

Page 203: ...ID8243 WAVEFORMS v X INSTRUCTION jf FLOAT f DATA j A A A A tip X V Xx OUTPUT Nf A A PREVIOUS OUTPUT VALID INPUT VALID PO XOUTPUT VALID X tcs 6 51 ...

Page 204: ... 5 TTL loads 1 6 mA assuming remaining pins are unloaded I 0L 5 x 1 6 mA 8 mA l 0L 60 mA from curve pins 60 mA 8 mA pin 7 5 7 In this case 7 lines can sink 8 mA for a total of 56 mA This leaves 4 mA sink current capa bility which can be divided in any way among the remaining 8 I O lines of the 8243 Example This example shows how the use of the 20 mA sink capability of Port 7 affects the sink ing c...

Page 205: ...c I TEST 1 INPUTS c p 8243 OUTPUT EXPANDER TIMING CDC ADDRESS 4 BITS DATA 4 BITS 00n READ 00 01 J WRITE 01 L P0RT 10 f OR 10 ADDRESS 11 AND 11_l CO oo 0 PROG P20 3 7T PROG P20 3 7 PROG P20 3 PROG P20 3 TT USING MULTIPLE 8243 s 6 53 ...

Page 206: ...e I O portion consists of 2 general purpose I O ports Each I O port has 8 port lines and each I O port line is indivdu ally programmable as input or output The 8355 2 has a 300ns access time for compatibility with the 8085A 2 microprocessor PIN CONFIGURATION BLOCK DIAGRAM CE C CE 2 C clkC RESET C N C NOT CONNECTED C READY C 10 MC ioSC RDC iowC aleC AD C AD C AD2 C AD3 C AD4 C AD5 C ad6 c AD C vssC...

Page 207: ...re 3 state If the latched Chip Enables are active a low on IOW causes the output port pointed to by the latched value of ADo to be written with the data on AD0 7 The state of IO M is ignored Symbol CLK Input READY Output PA0 7 Input Output PB0 7 Input Output RESET Input Tor Input Vcc Vss Function The CLK is used to force the READY into its high impedance state after it has been forced low by CE lo...

Page 208: ..._0 Output Leakage Current 10 ma 0 45V VOUT VCC cc Vcc Supply Current 180 mA A C CHARACTERISTICS TA o c to 70 c vcc 5V 5 Parameter 8355 8355 2 Preliminary Symbol Min Max Min Max Units tCYC Clock Cycle Time 320 320 ns T1 CLK Pulse Width 80 80 ns T2 CLK Pulse Width 120 120 ns tf tr CLK Rise and Fall Time 30 30 ns tAL Address to Latch Set Up Time 50 30 ns tLA Address Hold Time after Latch 80 30 ns tLC...

Page 209: ...8355 8355 2 Figure 1 Clock Specification for 8355 S 10 IO M ADo 7 zx a CE 0 CE2 1 J A I V ex x XI j c x A 1 I Figure 2 ROM Read and I O Read and Write 6 57 ...

Page 210: ... Mode RDOR 10 R J PORT INPUT DATA BUS 31 X x b Output Mode J W PORT OUTPUT X GLITCH FREE OUTPUT DATA BUS X X DATA BUS TIMING IS SHOWN IN FIGURE 4 Figure 3 I O Port Timing CE2 1 CE 0 Figure 4 Wait State Timing READY 0 6 58 ...

Page 211: ...rtion consists of 2 general purpose I O ports Each I O port has 8 port lines and each I O port line is individu ally programmable as input or output PIN CONFIGURATION BLOCK DIAGRAM PROG AND CE C 1 40 D VCC CE2 C 2 39 D PB7 CLK c 3 38 II PB6 RESET C 4 37 H PB5 VodC 5 36 D PB4 READY C 6 35 I PB3 IO M C 34 H PB2 iOR C 8 33 D PB i RD C 9 32 D PBo iow C 10 8755A 31 D PA7 ALE C 11 30 D PA6 AD C 12 29 D ...

Page 212: ...auses the output port pointed to by the latched value of ADo to be written with_the data on AD0 7 The state of IO M is ignored The CLK is used to force the READY into its high impedance state after it has been forced low by CE1 low CE2 high and ALE high Symbol READY output PA0 7 input output PBo 7 input output RESET input IOR input Vcc Vss Vdd Function READY isa_3 state output controlled by CE2 CE...

Page 213: ...e 8755A can be programmed on the Intel Universal PROM Programmer UPP and the PROMPT 80 85 and PROMPT 48 design aids The appropriate programming modules and adapters for use in programming both 8755A s and 8755 s are shown in Table 1 The program mode itself consists of programming a single address at a time giving a single 50 msec pulse for every address Generally it is desirable to have a verify c...

Page 214: ...in VCC to 0V Ilo Output Leakage Current 10 ma 0 45V V ut VCC cc Vqc Supply Current 180 mA A C CHARACTERISTICS ta o c to 70 c vcc 5V 5 SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS tCYC Clock Cycle Time 320 ns T1 CLK Pulse Width 80 ns Cload 150 pF T2 CLK Pulse Width 120 ns See Figure 3 tf t r CLK Rise and Fall Time 30 ns tAL Address to Latch Set Up Time 50 ns tLA Address Hold Time after Latch 80 n...

Page 215: ...WAVEFORMS 8755A Figure 2 Clock Specification for 8755A PROGl CE x A is y X f jg t Lc Please note that CEi must remain low tor the entire cycle X f X Figure 3 PROM Read I O Read and Write Timing 6 63 ...

Page 216: ...V I l PR H l RP PORT J INPUT y X J DATA BUS B OUTPUT MODE X IOW i GLITCH FREE Z OUTPUT PORT OUTPUT _y _ DATA BUS DATA BUS TIMING IS SHOWN IN FIGURE 4 X Figure 4 I O Port Timing CE 1 CE 0 A _ V Figure 5 Wait State Timing READY 0 6 64 ...

Page 217: ...5 26 V Idd Prog Supply Current 15 30 mA A C SPECIFICATION FOR PROGRAMMING Ta 0 C to 70 C Vcc 5V 5 Vss 0V Symbol Parameter Min Typ Max Unit tPS Data Setup Time 10 ns tPD Data Hold Time ns ts Prog Pulse Setup Time 2 MS tH Prog Pulse Hold Time 2 MS tPR Prog Pulse Rise Time 0 01 2 MS tPF Prog Pulse Fall Time 0 01 2 MS tPRG Prog Pulse Width 45 50 msec 6 65 ...

Page 218: ...55A WAVEFORMS PROGRAM CYCLE VERIFY CYCLE PROGRAM CYCLE A Dq 7 DGEDCX X X y A IOGEEX cdcz s VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE WITH VDD 5V FOR 8755A Figure 6 8755A Program Mode Timing Diagram 6 66 ...

Page 219: ...neral purpose I O ports One of the three ports can be programmed to be status pins thus allowing the other two ports to operate in handshake mode A 14 bit programmable counter timer is also included on chip to provide either a square wave or terminal count pulse for the CPU system depending on timer mode PIN CONFIGURATION pc3 c 1 40 3 vcc PC4 c 2 39 3 pc2 TIMER IN z 3 38 3 pc RESET c 4 37 3 pc pc5...

Page 220: ...Write control Input low on this line with the Chip Enable active causes the data on the Address Data bus to be written to the RAM or I O ports and command status register depending on IO M Symbol ALE input IO M input PA 7 8 input output PBo 7 8 input output PCo 5 6 input output TIMER IN input TIMER OUT output Vcc Vss Function Address Latch Enable This control signal latches both the add ress on th...

Page 221: ... portion See Figure 1 The 8 bit address on the Address Data lines Chip Enable input CE or CE and IO M are all latched on chip at the falling edge of ALE See Figure 2 7V L L_ 8 BIT INTERNAL DATA BUS T Tt f 7 77 i 2 7 L 77 L TIMER MSB it TIMER LSB TIMER MODE V V V J Figure 1 8155 8156 Internal Registers CE 8155 OR CE 8156 k IO M A 0 7 X ADDRESS y DATA VALID ALE RDORWR NOTE FOR DETAILED TIMING INFORM...

Page 222: ...ster since the command register shares the same I O address and the command register is selected when a write to that address is issued TM2 TM IEB IEA PC2 PC PB PA TIMER COMMAND DEFINES PA0 7 DEFINES PBq 7 DEFINES PC0 5 INPUT 1 OUTPUT ALT 1 ALT 2 ALT 3 ALT 4 ENABLE DISABLE 00 NOP DO NOT AFFECT COUNTER OPERATION 01 STOP NOP IF TIMER HAS NOT STARTED STOP COUNTING IF THE TIMER IS RUNNING 10 STOP AFTE...

Page 223: ...D2 and AD3 bits of the C S register When PC0 5 is used as a control port 3 bits are assigned for Port A and 3 for Port B The first bit is an interrupt that the 8155 sends out The second is an output signal indicating whether the buffer is full or empty and the third is an input pin to accept a strobe for the strobed input mode See Table 1 When the C port is programmed to either ALT3 or ALT4 the co...

Page 224: ... also that the output latch is cleared when the port enters the input mode The output latch cannot be loaded by writing to the port if the port is in the input mode The result is that each time a port mode is changed from input to output the output pins will go low When the 8155 56 is RESET the output latches are all cleared and all 3 ports enter the input mode When in the ALT 1 or ALT 2 modes the...

Page 225: ... timer is running STOP AFTER TC Stop immediately after present TC is reached NOP if timer has not started START Load mode and CNT length and start immediately after loading if timer is not presently running If timer is running start the new mode and CNT length immediately after present TC is reached NOTE 5 AND 4 REFER TO THE NUMBER OF CLOCKS IN THAT TIME PERIOD Figure 10 Asymmetrical Square Wave O...

Page 226: ... B Then call the following 8080A 8085A subroutine ADJUST 78 MOV A B Load accumulator with upper half of count E63F ANI 3F Reset upper 2 bits and clear carry 1F RAR Rotate right through carry 47 MOV B A Store shifted value back in B 79 MOV A C Load accumulator with lower half 1F RAR Rotate right through carry 4F MOV C A Store lower byte in C D0 RNC lf in 2nd half of count return lf in 1st half go o...

Page 227: ... CONFIGURATION Figure 11 shows a minimum system using three chips containing 256 Bytes RAM 2K Bytes POM 38 I O Pins 1 Interval Timer 4 Interrupt Levels NOTE OPTIONAL CONNECTIONS Figure 11 8085A Minimum System Configuration Memory Mapped I O 6 75 ...

Page 228: ...ve those indicated in the operational sections of this specifi cation is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability D C CHARACTERISTICS TA 0 C to 70 C Vcc 5V 5 SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 0 Vcc 0 5 V Vol Output Low Voltage 0 45 V Iol 2mA Voh Output High Vol...

Page 229: ...me 150 100 ns t WD Data In Hold Time After WRITE ns RV Recovery Time Between Controls 300 200 ns WP WRITE to Port Output 400 300 ns tpR Port Input Setup Time 70 50 ns tRP Port Input Hold Time 50 10 ns tSBF Strobe to Buffer Full 400 300 ns tss Strobe Width 200 150 ns RBE R EAD to Buffer Empty 400 300 ns tsi Strobe to INTR On 400 300 ns tRDI READ to INTR Off 400 300 ns tpss Port Setup Time to Strobe...

Page 230: ...8155 8156 8155 2 8156 2 WAVEFORMS a Read Cycle CE 8155 OR CE 8156 7 X X 7 X 7 X 7 X q 7 b Write Cycle CE 8155 OR CE 8156 7 s 7 x 7 X 7 X cn X 7 7 Figure 12 8155 8156 Read Write Timing Diagrams 6 78 ...

Page 231: ...81 55 81 56 81 55 2 81 56 2 a Strobed Input Mode INPUT DATA FROM PORT Z N X AJ b Strobed Output Mode OUTPUT DATA TO PORT Figure 13 Strobed I O Timing 6 79 ...

Page 232: ...DATA BUS TIMING IS SHOWN IN FIGURE 7 Figure 14 Basic I O Timing Waveform wp jx z c r LOAD COUNTER FROM CLR I 2 I TIMER OUT SQUARE WAVE NOTE 1 THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC RELOAD MODE M 1 MODE BIT 1 Figure 15 Timer Output Waveform Countdown from 5 to 1 6 80 ...

Page 233: ...provide a maximum level of system integration The low standby power dissipation minimizes system power requirements when the 8185 is disabled The 8185 2 is a high speed selected version of the 8185 PIN CONFIGURATION BLOCK DIAGRAM ADoC AD r ad2 AD3 C AD4 ADsC AD6 I AD7 8 11 VssC 9 D vcc 3 RD 3 WR 3 ALE J cs D CE2 PIN NAMES AD AD7 ADDRESS DATA LINES A8 A9 ADDRESS LINES CS CHIP SELECT CE1 CHIP ENABLE...

Page 234: ... keeping the 8185 powered down during I O and interrupt cycles TABLE 1 TRUTH TABLE FOR POWER DOWN AND FUNCTION ENABLE c CE2 CS CS l 2 l 8185 Status 1 X X Power Down and Function Disable X X Power Down and Function Disables 1 1 Powered Up and Function Disablefi 1 1 Powered Up and Enabled Notes X Don t Care 1 Function Disable implies Data Bus in high impedance state and not writing 2 CS CEi 0 CE2 1 ...

Page 235: ...t Leakage 10 MA Vin Vcc to 0V lLO Output Leakage Current 10 MA 0 45V Vout Vcc Ice Vcc Supply Current Powered Up Powered Down 100 mA 25 mA A C CHARACTERISTICS TA o c to 70 c vC c sv 5 Parameter 11 8185 Preliminary 8185 2 Preliminary Symbol Min Max Min Max Units tAL Address to Latch Set Up Time 50 30 ns t _A Address Hold Time After L atch 80 30 ns tLC Latch to READ WRITE Control 100 40 ns tRD Valid ...

Page 236: ...8185 8185 2 CEt O CE2 1 AD0 AD7 A8 A9 X f H 3 0 V ADDRESS Y V WP r w X t READCYCLEI WRITE CYCLE X Figure 2 8185 Timing 6 84 ...

Page 237: ...Chapter 7 ...

Page 238: ...ommon I O 7 5 2316E 16 384 Bit Static MOS ROM 7 9 2708 8192 1K x 8 EPROM 7 13 2716 16K UV Erasable PROM 7 16 5101 1024 Bit Static CMOS RAM 7 21 8205 High Speed 1 Out of 8 Binary Decoder 7 25 8212 Eight Bit Input Output Port 7 31 8214 Priority Interrupt Control Unit 7 41 8216 8226 4 Bit Parallel Bi Directional Bus Driver 7 45 ...

Page 239: ...TL compatible in all respects inputs outputs and a single 5V supply Two chip enables allow easy selection of an individual package when outputs are OR tied An output disable is provided so that data inputs and outputs can be tied for common I O systems The output disable function eliminates the need for bi directional logic in a common I O system The Intel 2101A is fabricated with N channel silico...

Page 240: ...bol Parameter Min TyP 11 Max Unit Test Conditions I LI Input Current 1 10 MA V N 0 to 5 25V loh Data Output Leakage Current 1 10 ma Output Disabled V ut 4 V lol Data Output Leakage Current 1 10 ma Output Disabled VO uT 0 45V cci Power Supply 2101A 2101A 4 35 55 mA V N 5 25V l 0mA Current 2101A 2 45 65 TA 25 C CC2 Power Supply 2101A 2101A 4 60 mA V N 5 25V l 0mA Current 2101A 2 70 TA 0 C V L Input ...

Page 241: ... ns tAW Write Delay 20 ns t r t f 20ns tew Chip Enable To Write 150 ns Input Levels 0 8V or 2 0V tow Data Setup 150 ns Timing Reference 1 5V tDH Data Hold ns Load 1 TTL Gate tW p Write Pulse 150 ns and CL 100pF tWR Write Recovery ns t DS Output Disable Setup 20 ns 2 CAPACITANCE ta 25 c f 1 MHz Symbol Test Limits pF Typ lD Max CIN Input Capacitance All Input Pins V N 0V 4 8 Qdut Output Capacitance ...

Page 242: ...Output Disable Setup 20 ns 2101A 4 450 ns ACCESS TIME A C CHARACTERISTICS READ CYCLE TA 0 C to 70 C Vcc 5V 5 unless otr erwise specified Symbol Parameter Min Typ Max Unit Test Conditions tRC Read Cycle 450 ns tA Access Time 450 ns tr t f 20ns tco Chip Enable To Output 310 ns Input Levels 0 8V or 2 0V l OD Output Disable To Output 250 ns Timing Reference 1 5V t DF I2J Data Output to High Z State 20...

Page 243: ...rge bit storage and simple interfacing are important design objectives It is directly TTL compatible in all respects inputs outputs and a single 5V supply Separate chip enable CE leads allow easy selection of an individual package when outputs are OR tied The Intel 21 1 1 A is fabricated with N channel silicon gate technology This technology allows the design and production of high performance eas...

Page 244: ...C Vrjc 5V 5 unless otherwise specified Symbol Parameter Min Typ tU Max Unit Test Conditions LI Input Load Current 1 10 MA V N to 5 25V loh I O Leakage Current 1 10 A Output Disabled V Q 4 0V lol I O Leakage Current 1 10 MA Output Disabled V o 0 45V cci Power Supply 21 11 A 21 11A 4 35 55 mA V N 5 25V Current 2111A 2 45 65 l 0 0mA TA 25 C CC2 Power Supply 21 11 A 211 1A 4 60 mA V N 5 25V Current 21...

Page 245: ...c Write Cycle 170 ns Uw Write Delay 20 ns tr tf 20ns tew Chip Enable To Write 150 ns Input Levels 0 8V or 2 0V tow Data Setup 150 ns Timing Reference 1 5V DH Data Hold ns Load 1 TTL Gate tWP Write Pulse 150 ns andCL 100pF tWR Write Recovery ns tos Output Disable Setup 20 ns 2 CAPACITANCE ta 25 c f 1MHz Symbol Test Limits pF TypJH Max CIN Input Capacitance All Input Pins V N 0V 4 8 C 0 I O Capacita...

Page 246: ... t DS Output Disable Setup 20 ns 2111A 4 450 ns ACCESS TIME A C CHARACTERISTICS READ CYCLE TA 0 C to 70 C VCc 5V 5 unless otherwise specified Symbol Parameter Min Typ Max Unit Test Conditions t RC Read Cycle 450 ns tA Access Time 450 ns t r tf 20ns tco Chip Enable To Output 310 ns Input Levels 0 8V or 2 0V tOD Output Disable To Output 250 ns Timing Reference 1 5V tDF I 2 Data Output to High Z Stat...

Page 247: ...ompatible Intel 2716 16K UV EPROM for prototyping and the lower cost 2616 PROM and 2316E ROM for production The three 2316E programmable chip selects may be defined by the user and are fixed during the masking process To simplify the conversion from 2716 prototyping to 2316E production it is recommended that the 2316E programmable chip select logic levels be defined the same as that shown in the b...

Page 248: ...e Current 20 MA Chip Deselected V ut 0 4V cc Power Supply Current 70 120 mA All Inputs 5 25V Data Out Open V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 4 VCC 1 0V V Vol Output Low Voltage 0 4 V I l 2 1 mA V H Output High Voltage 2 4 V Iqh 400 iA NOTE 1 Typical values for TA 25 C and nominal supply voltage A C CHARACTERISTICS TA 0 C to 70 C Vcc 5V 10 unless otherwise specified SYMBOL PA...

Page 249: ...A C Waveforms OUTPUT VALID Typical System Application 8K x 8 ROM Memory ADDRESS BUS MCS80 SYSTEM BUS CONTROL BUS Al2 An CHIP SELECT DECODER INTEL 8206 3 CSi a csl CS3 C CS2 CS3 7 Z CS2 CS3 XT 7 11 ...

Page 250: ...7 12 ...

Page 251: ...r microprocessors requiring fast access times For smaller size systems there is the 4096 bit 2704 which is organized as 512 words by 8 bits All these devices have the same programming and erasing specifications of the 2708 The 2704 electrical specifications are the same as the 2708 The 2708 family is fabricated with the N channel silicon gate FAMOS technology and is available in a 24 pin dual in l...

Page 252: ... 1 L imits 2708L Limits Units Symbol Mm TVP 21 Max Min Tvp 12 Max Test Conditions LI AddTess and Chip Select Input Sink Current 1 10 1 10 mA V N 5 25V or V N V L LO Output Leakage Current 1 10 1 10 mA vOUT 5 5V CS WE 5V lDDi3 VDD Supply Current 50 65 21 28 mA Worst Case Supply Currents ICCl3 Vcc Supply Current 6 10 2 4 mA All Inputs High lBBl3I Vbb Supply Current 30 45 10 14 mA CS WE 5V TA 0 C VlL...

Page 253: ...ccur when exposed to light with wave lengths shorter than approximately 4000 Angstroms A It should be noted that sunlight and certain types of fluores cent lamps have wavelengths in the 3000 4000A range Data show that constant exposure to room level fluores cent lighting could erase the typical device in approxi mately 3 years while it would take approximately 1 week to cause erasure when exposed ...

Page 254: ...e first EPROM with a static standby mode which reduces the power dissipation without increasing access time The maximum active power dissipation is 525 mW while the maximum standby power dissipation is only 132 mW a 75 savings The 2716 has the simplest and fastest method yet devised for programming EPROMs single pulse TTL level programming No need for high voltage pulsing because all programming c...

Page 255: ...ATION D C and Operating Characteristics Symbol Parameter Limits Unit Conditions Min Typ 31 Max Ili Input Load Current 10 MA V N 5 25V Ilo Output Leakage Current 10 IJiA Vqut 5 25V Ippi 2 Vpp Current 5 mA VPp 5 25V icci 2 Vcc Current Standby 10 25 mA CE V H OE V 1L l CC2 2 Vqc Current Active 57 100 mA 0 E CT V L V L Input Low Voltage 0 1 0 8 V V H Input High Voltage 2 0 Vcc 1 V Vol Output Low Volta...

Page 256: ... VO UT 0V A C Waveforms 1 ADDRESSES X ADDRESSES VALID CE 5 5 OUTPUT A C Test Conditions Output Load 1 TTL gate and C L 100 pF Input Rise and Fall Times 20 ns Input Pulse Levels 0 8V to 2 2V Timing Measurement Reference Level Inputs 1Vand2V Outputs 0 8V and 2V X tQH VALID OUTPUT 6 tDF HIGH Z NOTE 1 VfjC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp 2 Vpp may b...

Page 257: ...ilable for systems which require CE access of less than 450 ns for decode network operation The use of a PROM as a decoder allows for a Compatibility with upward and downward memory expansion b Easy assignment of ROM memory modules compatible with PL M modular software concepts 8K 16K 32K 64K 5V EPROM ROM FAMILY PRINTED CIRCUIT BOARD LAYOUT GND BN i 5 CfO 4 Cl e COMPONENT SIDE o e o _ 00 0 02 03 0...

Page 258: ...standby mode by applying a TTL high signal to the CE input When in standby mode the outputs are in a high impedence state independent of the OE input OUTPUT OR TIEING Because 271 6 s are usually used in larger memory arrays Intel has provided a 2 line control function that accomo dates this use of multiple memory connections The two line control function allows for a the lowest possible memory pow...

Page 259: ...minals An output disable function is provided so that the data inputs and outputs may be wire OR ed for use in common data I O systems The 5101L has the additional feature of guaranteed data retention at a power supply voltage as low as 2 0 volts A pin compatible N channel static RAM the Intel 2101 A is also available for low cost applications where a 256 X 4 organiza tion is needed The Intel ion ...

Page 260: ...s l L2 2 Input Current 5 5 nA IIloI 2 Output Leakage Current 1 1 juA CE1 2 2V V ut to VCC cci Operating Current 9 22 9 22 mA VIN VCC Except CE1 0 65V Outputs Open CC2 Operating Current 13 27 13 27 mA V N 2 2V Except CET 0 65V Outputs Open CCJ2 Standby Current 10 200 uA CE2 0 2V TA 70 C V L Input Low Voltage 0 3 0 65 0 3 0 65 V V H Input High Voltage 2 2 VCc 2 2 VCC V Vol Output Low Voltage 0 4 0 4...

Page 261: ...dress Change tOH2 Previous Read Data Valid with Respect to Chip Enable WRITE CYCLE t wc Write Cycle 450 650 AW Write Delay 130 150 tcwi Chip Enable CE 1 to Write 350 550 T CW2 Chip Enable CE 2 to Write 350 550 tow Data Setup 250 400 t DH Data Hold 50 100 t WP Write Pulse 250 400 t WR Write Recovery 50 50 DS Output Disable Setup 130 150 A C CONDITIONS OF TEST Input Pulse Levels 0 65 Volt to 2 2 Vol...

Page 262: ...EAD CYCLE ex 1 COMMON I O 111 x WRITE CYCLE y ADDRESS f X ca Jf NOTES 1 OD may be tied low for separate I O operation 2 During the write cycle OD is high for common I O and don t care for separate I O operation C _4 c 7 7 24 ...

Page 263: ...formance is specified over the temperature range of 0 C to 75 C ambient The use of Schottky barrier diode clamped transistors to obtain fast switching speeds results in higher performance than equivalent devices made with a gold diffu sion process PIN CONFIGURATION LOGIC SYMBOL A oC 1 16 K A CI 2 15 Z 0 A 2 CZ 3 14 ZDo E LI 4 8205 13 Z o2 e 2 L_ 5 12 _Jo3 E 3 C 6 11 Z o4 o 7 Z 7 10 Z 05 grd 8 9 Z ...

Page 264: ...bling signals so that the exclusive output of the decoded value is synchronous with the overall system The 8205 has a built in function for such gating The three enable inputs El E2 E3 are ANDed together and create a single enable signal for the decoder The combination of both active high and active low device enable inputs provides the designer with a powerfully flexible gating func tion to help ...

Page 265: ...uit to the I O port decoder an ar O El ray of 8205s can be used to create a simple interface to a 24K memory system The memory devices used can be either ROM or RAM and are 1K in storage capacity 8308s and 8102s are the devices typically used for this application This type of memory de vice has ten 10 address inputs and an active low chip select CS The lower order address bits A0 A9 which come fro...

Page 266: ... gates these signals with the clock phase 2 and the SYNC output of the 8008 CPU TheTT and T2 decoded strobes can connect directly to devices like 8212s for latching the address information The other de coded strobes can be used to generate signals to control the system data bus memory timing functions and interrupt structure RESET is connected to the enable gate so that strobes are not generated d...

Page 267: ...S TA 0 C to 75 C Vcc 5 0V 5 8205 PARAMETER LIMIT UNIT TEST CONDITIONS SYMBOL MIN MAX f INPUT LOAD CURRENT 0 25 inA Vrp 5 25V VF 0 45V r INPUT LEAKAGE CURRENT 10 uA Vcc 5 25V VR 5 25V vc INPUT FORWARD CLAMP VOLTAGE 1 0 V Vcc 4 75V l c 5 0 mA V OUTPUT LOW VOLTAGE 0 45 V Vcc 4 75V I QL 10 0 mA VOH OUTPUT HIGH VOLTAGE 2 4 V Vcc 4 75V 0H 1 5mA V INPUT LOW VOLTAGE 0 85 V VCC 5 0V VIH INPUT HIGH VOLTAGE ...

Page 268: ... 5 unless otherwise specified SYMBOL PARAMETER MAX LIMIT UNIT TEST CONDITIONS t ADDRESS OR ENABLE TO OUTPUT DELAY 18 ns t_ 18 ns t _ 18 18 ns t__ ns C 1 IN INPUT CAPACITANCE P8205 C8205 4 typ pF f 1 MHz VCC 0V 5 typ pF VBIAS 2 0V T a 25 C 1 This parameter is periodically sampled and is not 100 tested TYPICAL CHARACTERISTICS ADDRESS OR ENABLE TO OUTPUT DELAY VS LOAD CAPACITANCE cr S 10 go 50 100 15...

Page 269: ...ers Thus all of the principal peripheral and input output functions of a microcomputer system can be implemented with this device PIN CONFIGURATION r dsiC 1 24 J VCC Mor 2 23 Hint D iL 3 22 J DI 8 do iC 4 21 Jdo8 D 2 r 5 20 Hdi7 do2 l D 3 L 6 7 8212 19 18 Jdo7 JDI6 D03 L 8 17 d D 6 oi 4 r 9 16 3 DI 5 do l 10 15 Ido stbT 11 14 JCLR gndP 12 13 3 DS2 PIN NAMES Dl Die DOvDOb 1 DATA IN 1 bATAOUT OSi DS...

Page 270: ...s high output mode the output buffers are enabled and the source of clock C to the data latch is from the device selection logic DS1 DS2 When MD is low input mode the output buffer state is determined by the device selection logic DS1 DS2 and the source of clock C to the data latch is the STB Strobe input STB Strobe This input is used as the clock C to the data latch for the input mode MD 0 and to...

Page 271: ... The output to the data bus is symbolic in referencing 8 parallel lines BASIC SCHEMATIC SYMBOLS INPUT DEVICE OUTPUT DEVICE SYSTEM INPUT II Gated Buffer 3 State The simplest use of the 8212 is that of a gated buffer By tying the mode signal low and the strobe input high the data latch is acting as a straight through gate The output buffers are then enabled from the device selection logic DS1 and DS...

Page 272: ...ice request flip flop and interrupts the processor The processor then goes through a service routine identifies the port and causes the device selection logic to go true enabling the system input data onto the data bus INTERRUPTING INPUT PORT TO PRIORITY CKT ACTIVE LOW L y TO CPU INTERRUPT INPUT V Interrupt Instruction Port The 8212 can be used to gate the interrupt instruction normally RESTART in...

Page 273: ...TCH CONTROL DS1 DS2 VII 8080A Status Latch Here the 8212 is used as the status latch for an 8080A microcomputer system The input to the 8212 latch is directly from the 8080A data bus Timing shows that when the SYNC signal is true which is connected to the DS2 input and the phase 1 signal is true which is a TTL level coming from the clock generator then the status data will be latched into the 8212...

Page 274: ... in the cycle An address latch enable ALE signal is provided by the 8085A to be used by the 821 2 to latch the address so that it may be available through the whole machine cycle Note In this configuration the MODE input is tied high keeping the 8212 s output buffers turned on at all times Do Di D2 D3 D4 D5 D6 D7 DATA BUS Vcc 111 Dh STB Dd 8212 CLR DS MD DS 4 A b A 8 A2 IP A3 LOW ORDER lb t A4 ADD...

Page 275: ...y affect device reliability D C CHARACTERISTICS ta o c to 75 c vC c 5V 5 Symbol Parameter Limits Unit Test Conditions Min Typ Max If Input Load Current ACK DS2 CR DI1 DI8 Inputs 25 mA Vf 45V If Input Load Current MD Input 75 mA Vf 45V If Input Load Current DS1 Input 1 0 mA Vf 45V Ir Input Leakage Current ACK DS CR DI1 DI8 Inputs 10 HA Vr Vcc Ir Input Leakage Current MO Input 30 mA Vr Vcc Ir Input ...

Page 276: ...D 20 jys a o c INPUT VOLTAGE V OUTPUT LOW VOLTAGE V OUTPUT CURRENT VS OUTPUT HIGH VOLTAGE DATA TO OUTPUT DELAY VS LOAD CAPACITANCE 1 Vcc 5 V TA 25 C 1 t i I i i OUTPUT HIGH VOLTAGE V 50 100 150 200 250 300 LOAD CAPACITANCE pF DATA TO OUTPUT DELAY VS TEMPERATURE WRITE ENABLE TO OUTPUT DELAY VS TEMPERATURE 20 18 16 14 12 VCC 5 OV I J D 3 3 t o Vcc 50V I STB t DS 2 r IT s i L i TEMPERATURE I d TEMPER...

Page 277: ...Ta 25 C Symbol Test Limits Typ Max ClN DSi MD Input Capacitance 9pF 12pF ClN DS2 CK ACK DI i DIb Input Capacitance 5pF 9pF COUT DOi DOs Output Capacitance 8pF 12pF This parameter is sampled and not 100 tested SWITCHING CHARACTERISTICS Conditions of Test Input Pulse Amplitude 2 5V Input Rise and Fall Times 5ns Between 1V and 2V Measurements made at 1 5V with 15mA and 30pF Test Load Note 1 Test Load...

Page 278: ...TB or DSi DS2 DSt DS2 X 1 5V tpw 1 5V WE X J I X SEE NOTE BELOW v_ h D A 5V J_ W VOH s r h 1pw j v0L A X STB or DS DS2 DS1 DS2 1 5V f X1 5V l SET J tH J l PD X tpw NOTE ALTERNATIVE TEST LOAD Vcc R j 1 5V 1 5V 1 cl IK I 7 40 ...

Page 279: ...ction The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count in interrupt driven microcomputer systems Note The specifications for the 3214 are identical with those for the 8214 PIN CONFIGURATION LOGIC DIAGRAM c SGSQ INT Q clk inteQ GNOC 8214 24 D vcc 23 ici 22 3 21 3 20 3 19 3 18 3 17 3 16 3 15 1 14 ENLG 13 3 ETLG PIN NAMES INPUTS REQUEST LEVELS I...

Page 280: ...G CHARACTERISTICS TA 0 C to 70 C Vcc 5V 5 Symbol Parameter Limits Unit Conditions Min Typ Ml Max vc Input Clamp Voltage all inputs 1 0 V lc 5mA If Input Forward Current ETLG input all other inputs 15 08 0 5 0 25 mA mA VF 0 45V Ir Input Reverse Current ETLG input all other inputs 80 40 MA ma VR 5 25V Vil Input LOW Voltage all inputs 0 8 V VCC 5 0V V H Input HIGH Voltage all inputs 2 0 V VCC 5 0V cc...

Page 281: ... Ro R 7 Hold Time After CLK ns tics INT Setup Time to CLK 55 35 ns tci CLK to INT Propagation Delay 15 25 ns tRIS 141 R0 R7 Setup Time to fNT 10 ns tRIH l4 FVR7 Hold Time After INT 35 20 ns RA R0 R7 to A0 A2 Propagation Delay 80 100 ns ELA ELR to A A2 Propagation Delay 40 55 ns ECA ECS to A0 A2 Propagation Delay 100 120 ns ETA ETLG to A0 A2 Propagation Delay 35 70 ns tDECS141 SGS and B B Setup Tim...

Page 282: ...e The se times are not required for proper operation but for desired change in interrupt flip flop uired for new request or status to be properly loaded Test Conditions Input pulse amplitude 2 5 volts Input rise and fall times 5 ns between 1 and 2 volts Outpi t loading of 15 mA and 30 pf Speed measurements taken at the 1 5V levels Test Load Circuit 7 44 ...

Page 283: ...ctures the DB outputs provide a high 50 mA I l capability A non inverting 8216 and an inverting 8226 are available to meet a wide variety of applica tions for buffering in microcomputer systems Note The specifications for the 3216 3226 are identical with those for the 8216 8226 INN CONFIGURATION LOGIC DIAGRAM 8216 LOGIC DIAGRAM 8226 PIN NAMES OB DBj DATA BUS BIDIRECTIONAL W h DATA INPUT 0O DOj DAT...

Page 284: ...ovide maximum flexibility Of course they can be tied together so that the driver can be used to buffer a true bi directional bus such as the 8080 Data Bus The DO outputs on this side of the driver have a special high voltage output drive capability 3 65V so that direct interface to the 8080 and 8008 CPUs is achieved with an adequate amount of noise immunity 350m V worst case Control Gating DIEN CS...

Page 285: ...2 volts Output loading is 5 mA and 10 pF Speed measurements are made at 1 5 volt levels Test Load Circuit CAPACITANCES Parameter Limits Symbol Min Typ m Max Unit CIN Input Capacitance 4 8 PF COUT1 Output Capacitance 6 W pF CquT2 Output Capacitance 13 18 pF Test Conditions VBIAS 2 5V Vcc 5 0V TA 25 C f 1 MHz NOTES 1 Typical values are for TA 25 C Vqq 5 0V 2 DO Outpuw CL 30pF Rj 300 10 Kn R2 180 IKf...

Page 286: ...r Limits Unit Symbol Min Typ Max Conditions fi Input Load Current DIEN CS 0 15 5 mA VF 0 45 F2 Input Load Current All Other Inputs 0 08 25 mA VF 0 45 ri Input Leakage Current DIEN CS 80 juA VR 5 25V r2 Input Leakage Current Dl Inputs 40 MA VR 5 25V vc Input Forward Voltage Clamp 1 V lc 5mA Vil Input Low Voltage 95 V V H Input High Voltage 2 0 V Hol Output Leakage Current DO 3 State DB 20 100 MA V ...

Page 287: ... when a Hold request has been acknowledged during a DMA activity Memory and I O Interface to a Bidirectional Bus In large microcomputer systems it is often necessary to pro vide Memory and I O with their own buffers and at the same time maintain a direct common interface to a bi directional Data Bus The 8216 8226 has separated data in and data out lines on one side and a common bi directional set ...

Page 288: ......

Page 289: ...Chapter 8 PERIPHERALS ...

Page 290: ...ble Interrupt Controller 8 41 8273 Programmable HDLC SDLC Controller 8 59 8278 Programmable Keyboard Interface 8 62 8279 8279 5 Programmable Keyboard Display Interface 8 72 8291 GPIB Talker Listener 8 84 8292 GPIB Controller 8 108 8294 Data Encryption Unit 8 110 8295 Dot Matrix Printer Controller 8 111 8041 8741 A Universal Peripheral Interface 8 Bit Microcomputer 8 112 ...

Page 291: ...CPU The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has received a character for the CPU The CPU can read the complete status of the USART at any time These include data transmission errors and control signals such as SYNDET TxEMPTY The chip is constructed using N channel silicon gate technology Asynchronous Baud Rate DC to 19 2K Baud Full Duple...

Page 292: ...nclusion of a transmission TxD line will always return to the marking state unless SBRK is programmed Tx Enable logic enhancement prevents a Tx Disable command from halting trans mission until all data previously written has been transmitted The logic also prevents the transmitter from turning off in the middle of a word When External Sync Detect is programmed Internal Sync Detect is disabled and ...

Page 293: ...mitter Enable bit is set in the Command Instruction and it has received a Clear To Send CTS input TneTxD output will be held in the marking state upon Reset Programming the 8251 Prior to starting data transmission or reception the 8251A must be loaded with a set of control words generated by the CPU These control signals define the complete func tional definition of the 8251A and must immediately ...

Page 294: ...ode synchronization is achieved by applying a high level on the SYNDET pin thus forcing the 8251 A out of the HUNT mode The high level can be removed after one RxC cycle An ENTER HUNT command has no effect in the asynchronous mode of operation Parity error and overrun error are both checked in the same way as in the Asynchronous Rx mode Parity is checked when not in Hunt regardless of whether the ...

Page 295: ...ditions for extended periods may affect device reliability D C CHARACTERISTICS TA 0 C to 70 C VCc 5 0V 5 GND 0V Symbol Parameter Min Max Unit Test Conditions V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 2 VCC V Vol Output Low Voltage 0 45 V Iql 2 2 mA Voh Output High Voltage 2 4 V Iqh 400mA OFL Output Float Leakage 10 ma V UT VCC TO 0 45V lL Input Leakage 10 HA Vin VCC TO 0 45V cc Powe...

Page 296: ...RITE 50 ns WA Address Hold Time for WRITE 50 ns ww WRITE Pulse Width 250 ns DW Data Set Up Time for WRITE 150 ns WD Data Hold Time for WRITE 30 ns tRV Recovery Time Between WRITES 6 tCY Note 4 NOTES 1 AC timings measured VrjH 2 0 Vol 0 8 and with load circuit of Figure 1 2 Chip Select CS and Command Data C D are considered as Addresses 3 Assumes that Address is valid before Rd 4 This recovery time...

Page 297: ...d 64x Baud Rate 1 tCY RPD Receiver Input Clock Pulse Delay 1x Baud Rate 15 CY 16x and 64x Baud Rate 3 CY tTxRDY TxRDY Pin Delay from Center of last Bit 8 CY Note 7 TxRDY CLEAR TxRDY from Leading Edge of WR 180 ns Note 7 tRxRDY RxRDY Pin Delay from Center of last Bit 24 CY Note 7 tR xRDY CLEAR RxRDY 4 from Leading Edge of RD 150 ns Note 7 tis Internal SYNDET Delay from Rising Edge of RxC 24 CY Note...

Page 298: ...aQQcaTHmnDQacrumrioacr Jt 4 X J _ _ Transmitter Control Flag Timing SYNC Mode J l 1 f EXAMPLE FORMAT 5 BIT CHARACTER WITH PARITY 2 SYNC CHARACTERS Receiver Control Flag Timing SYNC Mode EXIT HUNT MODE SET SYN DET STATUS BIT SET SYNDET STATUS BIT 8 8 0021 6A ...

Page 299: ...ation are soft ware programmable PIN CONFIGURATION BLOCK DIAGRAM D7 C CLK0 OUT0 GATEOl GNDl 6 8253 is C 9 C 10 C 11 C 12 3vcc Uwr 3rd 3cs 3a I a UCLK2 3 OUT 2 J GATE 2 DCLK 1 3 GATE 1 DOUT1 PIN NAMES D7 D DATA BUS 8 BIT CLK N COUNTER CLOCK INPUTS GATE N COUNTER GATE INPUTS OUT N COUNTER OUTPUTS RD READ COUNTER WR WRITE COMMAND OR DATA CS CHIP SELECT An A COUNTER SELECT Vcr 5 VOLTS GND GROUND READ ...

Page 300: ...PU instructions The Data Bus Buffer has three basic functions 1 Programming the MODES of the 8253 2 Loading the count registers 3 Reading the count values Read Write Logic The Read Write Logic accepts inputs from the system bus and in turn generates control signals for overall device operation It is enabled or disabled by CS so that no operation can occur to change the function unless the device h...

Page 301: ...or these functions The reading of the contents of each counter is available to the programmer with simple READ operations for event counting applications and special commands and logic are included in the 8253 so that the contents of each counter can be read on the fly without having to inhibit the clock input 8253 SYSTEM INTERFACE The 8253 is a component of the Intel Microcomputer Systems and int...

Page 302: ...t then most significant byte M2 M1 MO ModeO 1 Mode 1 X 1 Mode 2 X 1 1 Mode 3 1 Mode 4 1 1 Mode 5 BCD Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades Counter Loading The count register is not loaded until the count value is written one or two bytes depending on the mode selected by the RL bits followed by a rising edge and a falling edge of the clock Any read of the counter prio...

Page 303: ... low and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by 2 until timeout Then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts MODE 4 Software Triggered Strobe After the mode is set the output will be high When the count is ...

Page 304: ...T n 5 S4252S4252542 J 1 I J MODE 1 Programmable One Shot clock JTJIJTJIJTJTJTJTJTJIJXriJI WRn TRIGGER OUTPUT TRIGGER _ OUTPUT 4 3 2 10 n 4 L 4 3 2 4 3 2 10 MODE 4 Software Triggered Strobe clock jxnjiJiJijTjTJijijnjTrLrL OUTPUT LOAD n GATE OUTPUT n 4 r 4 3 2 10 t r 4 3 2 10 MODE 2 Rate Generator cLocK_njTjxiXTTJTJTJTJTJTJTXLJTJTJT_ 0 3 OUTPUT n 31 LJ MODE 5 Hardware Triggered Strobe clock JTJIJIJT...

Page 305: ... time following the MODE control word loading as long as the correct number of bytes is loaded in order All counters are down counters Thus the value loaded into the count register will actually be decremented Loading all zeroes into a count register wiH result in the maximum count 2 16 for Binary or 104 for BCD In MODE the new count will not restart until the load has been completed It will accep...

Page 306: ... the entire reading procedure If two bytes are programmed to be read then two bytes must be read before any loading WR command can be sent to the same counter Read Operation Chart A1 AO RD Read Counter No 1 Read Counter No 1 1 Read Counter No 2 1 1 Illegal Reading While Counting In order for the programmer to read the contents of any counter without effecting or disturbing the counting operation t...

Page 307: ...ute maximum rating conditions for extended periods may affect device reliability D C CHARACTERISTICS ta oc to o c vcc 5V 5 SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 2 VCC 5V V Vol Output Low Voltage 0 45 V Note 1 Voh Output High Voltage 2 4 V Note 2 IlL Input Load Current 10 A A Vim Vcc to 0V OFL Output Float Leakage 10 IJ A Vqut VCc to...

Page 308: ...ny Other Control Signal 1 1 AS Write Cycle SYMBOL PARAMETER 82 MIN 53 MAX 8253 5 MIN MAX UNIT 50 30 AW Address Stable Before WRITE ns WA Address Hold Time for WR ITE 30 30 ns WW WRITE Pulse Width 400 300 ns tDW Data Set Up Time for WR ITE 300 250 ns twD Data Hold Time for WRITE 40 30 ns 1 1 tRV Recovery Time Between WRITE and Any Other Control Signal MS Notes 1 AC timings measuredat Vqh 2 2 Vol 0 ...

Page 309: ...230 230 ns tPWL Low Pulse Width 150 150 ns tGW Gate Width High 150 150 ns tGL Gate Width Low 100 100 ns GS Gate Set Up Time to CLKt 100 100 ns tGH Gate Hold Time After CLKt 50 50 ns OD Output Delay From CLK M 1 400 400 ns tQDG Output Delay From Gatei 1 300 300 ns Note 1 Test Conditions 8253 Cl 100pF 8253 5 C _ 150pF _ I WL OD u X 8 19 00745A ...

Page 310: ...of input or output Of the remaining 4 pins 3 are used for hand shaking and interrupt control signals The third mode of operation MODE 2 is a bidirectional bus mode which uses 8 lines for a bidirectional bus and 5 lines borrowing one from the other group for handshaking PIN CONFIGURATION PA3 C W 40 PA2 C 39 PAlC 38 I PAO C 37 Z RD 36 Z cs C 6 35 z GND G 34 z C 8 33 z ao r 9 32 z PC7 Q PC6Q 10 8255A...

Page 311: ...n issues commands to both of the Control Groups CS Chip Select A low on this input pin enables the com muniction between the 8255A and the CPU RD Read A low on this input pin enables the 8255A to send the data or status information to the CPU on the data bus In essence it allows the CPU to read from the 8255A WR Write A low on this input pin enables the CPU to write data or control words into the ...

Page 312: ...to further enhance the power and flexibility of the 8255A Port A One 8 bit data output latch buffer and one 8 bit data input latch Port B One 8 bit data input output latch buffer and one 8 bit data input buffer Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a ...

Page 313: ...u tational results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis ADDRESS BUS CONTROL BUS Ji n Ji RD WR tVDo A A CS 8255A i B C A J 8 WO J 4 h o J 4 M O 1 8 w PB7 PB PC3 PC PC7 PC4 PA7 PA MODE 1 T_B_ PB7 PB CONTROL CONTROL PA7 PA OR I O OR I O MODE 2 J B I 8 I O PB7 PB I O A T 8 BIDIRECTIONAL J PA PA Figure 3 Basic Mode Definitions and Bus I...

Page 314: ...tion allows the Programmer to disallow or allow a specific I O device to interrupt the CPU without affecting any other device in the interrupt structure INTE flip flop definition BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Note All Mask flip flops are automatically reset during mode selection and device Reset Operating Modes MODE Basic Input Output This functiona...

Page 315: ...PUT 1 1 OUTPUT INPUT 6 INPUT OUTPUT 1 1 1 OUTPUT INPUT 7 INPUT INPUT INPUT OUTPUT 8 OUTPUT OUTPUT 1 INPUT OUTPUT 9 OUTPUT INPUT 1 INPUT OUTPUT 10 INPUT OUTPUT 1 1 INPUT OUTPUT 11 INPUT INPUT 1 INPUT INPUT 12 OUTPUT OUTPUT 1 1 INPUT INPUT 13 OUTPUT INPUT 1 1 INPUT INPUT 14 INPUT OUTPUT 1 1 1 INPUT INPUT 15 INPUT INPUT MODE Configurations CONTROL WORD 0 7 D6 D5 D4 D3 D2 D1 D CONTROL WORD 1 yi PA7 PA...

Page 316: ... D 10 10 1 CONTROL WORD 9 D7 D6 D5 D4 D3 D2 D1 D 10 7 P 7 A i PC7 PC4 PA7 PA PC7 PC4 7 PC3 PC PB7 PB PC3 PC CONTROL WORD 6 D7 D6 D5 D4 3 D2 D1 D 10 10 10 CONTROL WORD 10 D7 D6 D5 D4 D3 D2 D D 10 10 Z1 PAj PA 7 PC7 7 PCj PC PA7 PA PC7 PC4 F pc3 pc CONTROL WORD 7 CONTROL WORD 11 D7 Dg D5 D4 D3 D2 D Dp 10 10 11 D7 Dg D5 D4 D3 D2 D D 10 10 11 PA7 PA A pc7 pc4 Z1 wyPA PC7 PC4 pc3 pc pb7 pb V O 8 26 007...

Page 317: ...nal con figuration provides a means for transferring I O data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 port A and Port B use the lines on port C to generate or accept these hand shaking signals Mode 1 Basic Functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port...

Page 318: ...output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to request service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC 4 INTEB Controlled by bit set reset of PC 2 MODE 1 PORT A CONTR...

Page 319: ...hat it has received the data output by the CPU INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has ac cepted data transmitted by the CPU INTR is set when ACK is a one OBF is a one and INTE is a one It is reset by the falling edge of WR INTE A Controlled by bit set reset of PCg INTEB Controlled by bit set reset of PC 2 MODE 1 PORT A CONTROL WORD 7...

Page 320: ...available OBF Output Buffer Ful The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of port A to send out the data Otherwise the output buffer will be in the high im pedance state MODE 2 Basic Functional Definitions Used in Group A only One 8 bit bi directional bus Port Port A and a 5 bit control...

Page 321: ...re 11 MODE Control Word Figure 12 MODE 2 PERIPHERAL BUS DATA FROM CPU TO 82S5A I t_ DATA FROM PERIPHERAL TO 8255A r DATA FROM j 8255A TO PERIPHERAL DATA FROM 82SSA TO 8080 Figure 13 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF MASK STB RD OBF MASK ACK WR 8 31 00744A ...

Page 322: ...MXM I Q H J PA PAo OOOBFA ACKA I O MODE 2 AND MODE 1 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD D7 D6 D5 D4 D3 D2 D D JM pc3 PA7 PA PC7 PC6 PC4 PC5 PB7 PB PC PC2 r V PC CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D h h IXIXIX1 h C l PA7 PAo PC7 N v 61FA pc6 PC4 ACKA st a PC5 PB7 PB C IBFA 8 1 PC STBg IBFB pc INTR Figure 14 MODE 2 Combinations 8 32 00744A ...

Page 323: ...reset function or accessed as a threesome by writing into Port C Source Current Capability on Port B and Port C Any set of eight output buffers selected randomly from Ports B and C can source 1mA at 1 5 volts This feature allows the 8255 to directly drive Darlington type drivers and high voltage displays that require such source current Reading Port C Status In Mode 0 Port C transfers data to or f...

Page 324: ... 8255A to exactly fit the applica tion Figures 17 through 23 present a few examples of typical applications of the 8255A INTERRUPT REQUEST MODE1 OUTPUT MODE1 OUTPUT PAo INTERRUPT REQUEST 3 DATA READY ACK PAPER FEED FORWARD REV DATA READY ACK HIGHSPEED PRINTER HAMMER RELAYS DATA READY ACK PAPER FEED FORWARD REV RIBBON CARRIAGE SEN CONTROL LOGIC AND DRIVERS Figure 17 Printer Interface INTERRUPT REQU...

Page 325: ...C TEST BUSY LT SAMPLE EN STB LSB 8 BIT AD CONVERTER ADC MSB ANALOG INPUT I Figure 20 Digital to Analog Analog to Digital Figure 22 Basic Floppy Disc Interface INTERRUPT REQUEST PAo MODE 1 _j OUTPUT 1 MODE _ OUTPUT INTERRUPT REQUEST CRT CONTROLLER CHARACTER GEN REFRESH BUFFER CURSOR CONTROL SHIFT CONTROL DATA READY ACK BLANKED BLACK WHITE ROW STB COLUMN STB CURSOR H V STB CURSOR ROW COLUMN ADDRESS ...

Page 326: ...IT TEST CONDITIONS V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 0 vCc V Vol DB Output Low Voltage Data Bus 0 45 V Iol 2 5mA Vol PER Output Low Voltage Peripheral Port 0 45 V Iol 1 7mA Voh DB Output High Voltage Data Bus 2 4 V lOH 400mA Voh PER Output High Voltage Peripheral Port 2 4 V Ioh 200 uA IdarI 1 Darlington Drive Current 1 0 4 0 mA R E XT 750ft VE xT 1 5V cc Power Supply Current...

Page 327: ...WD Data Valid After WRITE 30 30 ns Other Timings PARAMETER 8255A 8255A 5 SYMBOL MIN MAX MIN MAX UNIT t VB WR 1 to Output 1 350 350 ns t R Peripheral Data Before RD ns HR Peripheral Data After RD ns T AK ACK Pulse Width 300 300 ns tST STB Pulse Width 500 500 ns tps Per Data Before T E of STB ns tPH Per Data After T E of STB 180 180 ns tAD ACK 0toOutputl 1 l 300 300 ns l KD ACK 1 to Output Float 20 ...

Page 328: ...8255A 8255A 5 J TEST POINTS Y o 8 o 8 A Figure 25 Input Waveforms for A C Tests X X l c X Z3C Figure 26 MODE Basic Input X ww J c WD K _tWA X WB zx Figure 27 MODE Basic Output 8 38 00744A ...

Page 329: ...8255A 8255A 5 INPUT FROM PERIPHERAL c ST _y i f f R T Y V Figure 28 MODE 1 Strobed Inut Figure 29 MODE 1 Strobed Output 8 39 00744A ...

Page 330: ... 5 PERIPHERAL BUS DATA FROM PERIPHERAL TO 8255 Figure 30 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occu rs before R D is permissible INTR IBF MASK STB RD OBF MASK ACK WR 8 40 00744A ...

Page 331: ... is fully upward compatible with the Intel 8259 Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes MCS 80 85 Non Buffered Edge Triggered PIN CONFIGURATION BLOCK DIAGRAM csC wrC rdC D C CASOC CAS1 C gndC 1 28 wcc 2 27 3 3 26 Uinta 4 25 DlR7 5 24 UIR6 6 23 DlR5 7 22 8259A 8 21 UlR4 DlR3 9 20 3 IR2 10 19 UlRI 11 18 UlRO 12 17 J INT 13 16 D SP EN 14 15 13 CAS ...

Page 332: ...r enhance its cost effectiveness The Programmable Interrupt Controller PIC functions as an overall manager in an Interrupt Driven system environment It accepts requests from the peripheral equipment determines which of the incoming requests is of the highest importance priority ascertains whether the incoming request has a higher priority value than the level currently being serviced and issues an...

Page 333: ...This 3 state bidirectional 8 bit buffer is used to inter face the 8259A to the system Data Bus Control words and status information are transferred through the Data Bus Buffer READ WRITE CONTROL LOGIC The function of this block is to accept OUTput com mands from the CPU It contains the Initialization Com mand Word ICW registers and Operation Command Word OCW registers which store the various contr...

Page 334: ...o be sent to the 8259A from the CPU group 6 These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus The lower 8 bit address is released at the first INTA pulse and and the h igher 8 bit address is re leased at the second INTA pulse 7 This completes the 3 byte CALL instruction released by the 8259A In the AEOI mode the ISR bit is reset at the end of t...

Page 335: ...the bus Content of Third Interrupt Vector Byte D6 OS 04 03 02 D1 00 A14 A13 A12 A11 A10 A8 MCS 86 SYSTEM MCS 86 mode is similar to MCS 80 mode except that only two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the proc essor The first interrupt acknowledge cycle is similar to that of MCS 80 85 systems in that the 8259A uses it to internally freeze the state...

Page 336: ...e Interrupt Mask Register is cleared b IR 7 input is assigned priority 7 c The slave mode address is set to 7 d Special Mask Mode is cleared and Status Read is set to IRR e If IC4 0 then all functions selected in ICW4 are set to zero Non Buffered mode no Auto EOI MCS 80 85 system non SFNM The OCWs can be written into the 8259A anytime after initialization Not Master Slave in ICW4 is only used in t...

Page 337: ... be read If ICW4 is not needed set IC4 0 INITIALIZATION COMMAND WORD 3 ICW3 This word is read only when there is more than one 8259A in the system and cascading is used in which case SNGL 0 It will load the 8 bit slave register The functions of this register are a In the master mode either when SP 1 or in buffered mode when M S 1 in ICW4 a 1 is set for each slave in the system The master then will...

Page 338: ...R DEVICE Ao D 6 D4 3 2 D b 1 S h S S3 s s So 1 IR INPUT HAS A SLAVE IR INPUT DOES NOT HAVE A SLAVE ICW3 SLAVE DEVICE 0 D4 3 D2 1 ID ID ID SLAVE IDI 1 2 3 4 s 6 7 1 1 1 1 1 1 1 1 1 1 1 1 AO D7 06 D5 D4 D3 02 D 1 DO 1 FNM BUF M S AEOI FM 1 MCS 86 MODE MCS 80 85 MODE 1 AUTO EOI 0 NORMAL EOI NON BUFFERED MODE BUFFERED MODE SLAVE BUFFERED MODE MASTER 1 X 1 1 1 FULLY NESTED MODE NOT F JLLY NESTED MODE N...

Page 339: ...es the channel is masked inhibited M indicates the channel is enabled OPERATION CONTROL WORD 2 OCW2 R SEOI EOI These three bits control the Rotate and End of Interrupt modes and combinations of the two A chart of these combinations can be found on the Opera tion Command Word Format L2 Li Lq These bits determine the interrupt level acted upon when the SEOI bit is active m m SEOI EOI SRIS RIS OPERAT...

Page 340: ...DE A ROTATE AT EOI MODE Bl L0 L2 DEFINES NEW LOWEST PRIORITY SET ROTATE A FF CLEAR ROTATE A FF ROTATE PRIORITY MODE B INDEPENDENTLY OF EOI IL0 L2CODE OF LINE NO OPERATION 1 1 1 1 1 1 1 1 1 c 1 1 1 D D6 Dj D4 3 D O Dj ESMM SMM 1 P ERIS RIS READ IN SERVICE REGISTER READ IR REG ON NEXT RD PULSE READ IS REG ON NEXT RD PULSE A HIGH ENABLES THE NEXT RD PULSE TO READ THE BCD CODE OF THE HIGH EST LEVEL RE...

Page 341: ...NESTED MODE This mode is entered after initialization unless another mode is programmed The interrupt requests are ordered in priority form through 7 0 highest When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus Additional ly a bit of the Interrupt Service register ISO 7 is set This bit remains set until the microprocessor issues an End of ...

Page 342: ...at is masked by an IMR bit will not be cleared by a non specific EOI if the 8259A is in the Special Mask Mode AUTOMATIC END OF INTERRUPT AEOI MODE If AEOI 1 in ICW4 then the 8259A will operate in AEOI mode continuously until reprogrammed by ICW4 In this mode the 8259A will automatically perform a non specific EOI operation at the trailing edge of the last interrupt acknowledge pulse third pulse in...

Page 343: ...n the system The following registers can be read by issuing a suitable OCW3 and reading with RD Interrupt Mask Register 8 bit register whose content specifies the interrupt request lines being masked acknowledged The highest request level is reset from the IRR when an interrupt is acknowledged Not affected by IMR In Service Register ISR 8 bit register which contains the priority levels that are be...

Page 344: ...at 8 single edge triggered Format 8 single level triggered Format 8 not single edge triggered Format 8 not single level triggered Format 4 single edge triggered Format 4 single level triggered Format 4 not single edge triggered Format 4 not single level triggered Format 8 single edge triggered Format 8 single level triggered Format 8 not single edge triggered Format 8 not single level triggered By...

Page 345: ...86 The IRO input should not be connected to a slave 8259A unless IR1 IR7 also have slaves attached The cascade bus lines are normally low and will contain the s lave address code from the trailing edge of the first INTA pulse to the trailing edge of the third pulse It is obvious that each 8259A in the system must follow a separate initialization sequence and can be pro grammed to work in a differe...

Page 346: ...can be read CS is active LOW 17 Goes directly to the micro processor interrrupt input This output will have high V h to match the 8080 3 3V V H INT is active HIGH 12 Three cascade lines outputs in 13 master mode and inputs in slave 15 mode The master issues the binary code of the acknowledged interrupt level on these lines Each slave compares this code with its own 16 SP EN is a dual function pin ...

Page 347: ...ote 1 This Is the low time required to clear the Input latch m the edge triggered mode TIMING RESPONSES 8259A 8 8259A Symbol Parameter Mln Max Mln Max Units Test Conditions TRLDV Data Valid from RD INTA4 300 200 ns C of Data Bus TRHDZ Data Float after RD iNTAt 10 200 100 ns Max test C 100 pF TJHIH Interrupt Output Delay 400 350 ns Min test C 15 pF TIALCV Cascade Valid from First INTAI Master Only ...

Page 348: ...8259A WRITE MODE ADDRESS BUS Ae DATA BUS READ INTA MODE RCMNTA ro es ADDRESS BUS Ae OTHER TIMING KD INTA WR INTA SEQUENCE X X X X X X i f X A trhrl f INT JNTA v i nvi to o TCVI VDV f TCVIAL 1 8 58 ...

Page 349: ...6 3 PB7 TxDRQ C 6 35 3 RTS RxDACK C 7 34 2 pa7 RxDRQ C 8 33 2 PA So C 9 32 3 PA WR C 10 8273 31 3 CD Rx INT C 30 3 5TS DBO C 12 29 3 TxD OB1 C 13 28 2 TxC DB2 C 14 27 2 RxC DB3 C 15 26 3 RxD DB4 C 16 25 3 32xCLK DB5 C 17 24 3 CS DB6 fj 18 23 1 OPLL DB7 19 22 3 Al GND 20 21 3 PIN NAMES DBO DB7 FLAG DET TxINT CLK RESET Tx DACK TxDRQ RB Bfi Rx DACK RxDRQ RxINT A0 A1 BFCl DATA BUS 8 BITS FLAG DETECT T...

Page 350: ...urposes and a Non sequenced Frame is used for initialization and control of the secondary stations Frame Characteristics An important characteristic of a frame is that its con tents are made code transparent by use of a zero bit insertion and deletion technique Thus the user can adopt any format or code suitable for his system it may even be a computer word length or a memory dump The frame is bit...

Page 351: ...ines which in terface with the system Data Bus I The Write signal is used to con trol the transfer of either a com mand or data from CPU to the 8273 RD 9 I The Read signal is used to con trol the transfer of either a data byte or a status word from the 8273 to the CPU TxINT 2 O The Transmitter interrupt signal indicates that the transmitter logic requires service RxlNT H O The Receiver interrupt s...

Page 352: ...c displays and simple indicators may be used The 8278 has a 16X4 display RAM which can be loaded or interrogated by the CPU Both right entry calculator and left en try typewriter display formats are possible Both read and write of the display RAM can be done with auto increment of the display RAM address PIN CONFIGURATION PIN NAMES BLOCK DIAGRAM RLC y 40 Dvcc xi C 2 39 UCLR X2 2 3 38 HB3 RESET C 4...

Page 353: ...e keyboard col umn scan The outputs are for multiplexed digital displays Signal Pin No Description ERROR 24 Error signal This line is high when ever two new key closures are de tected during a single scan or when too many characters are entered into the keyboard FIFO It is reset by a system RESET pulse or by a 1 input on the CLR pin or by the CLEAR ERROR command CLR 39 Input used to clear an ERROR...

Page 354: ...the FIFO and whether it is full or empty Too many reads or key entries will be recognized as an error The status can be read by a RD with CS low and Ao high The status logic also provides a IRQ signal to the master processor whenever the FIFO is not empty Display Address Registers and Display RAM The display Address registers hold the address of the word currently being written or read by the CPU ...

Page 355: ...error on multiple key depression 1 no error on multiple key depression N the number of display digits select 0 16 display digits 1 8 display digits NOTE The default mode following a RESET input is all bits zero 1 I 1 Read F IFO Command CODE 1 Read Cdisplay Command CODE 1 1 Al A3 A2 Ai Ao Where Al indicates Auto Increment and A3 A0 is the address of the next display character to be written Clear Bl...

Page 356: ...cter read will be the last one entered FIFO status will remain at 0000 and the error condition will not be set Data Read Sequence Before reading data the master CPU must send a command to select FIFO or Display data Following the command the master must read STATUS and test the BUSY flag and the OBF flag to verify that the 8278 has responded to the previous command A typical DATA READ sequence is ...

Page 357: ... word the TONE output is activated and IRQ is set and no further inputs are accepted This condition is cleared by a high signal on the CLEAR input or by a system RESET input or by the CLEAR ERROR command In the special function mode both the key closure and the key release cause an entry to the FIFO The release is entered with the MSB 1 Any key entry triggers the TONE output for 10ms The HYS and K...

Page 358: ...ress in the RAM is the left most display character and address 15 is the right most display character Entering characters from position zero causes the display to fill from the left The 17th character is entered back in the left most position and filling again proceeds from there Right Entry Right entry is the method used by most electronic calculators The first entry is placed in the right most d...

Page 359: ...REMENT 12 3 4 5 6 7 3RD ENTRY 1 2 3 1 2 3 4 5 6 7 4TH ENTRY 1 2 3 4 In the Right Entry mode Auto Incrementing and non Incrementing have the same effect as in the Left Entry except that the address sequence is interrupted 1 2 3 4 5 6 7 0 DISPLAY RAM 1ST ENTRY ADDRESS 2 3 4 5 6 7 1 2ND ENTRY I 1 2 2 3 4 5 6 7 1 COMMAND 10010101 1 2 ENTER NEXT AT LOCATION 5 AUTO INCREMENT 3 4 5 6 7 12 3RD ENTRY 3 1 2...

Page 360: ...C Vcc 5V 5 Vss 0V Symbol Parameter Min Max Units Condition VlL Input Low Voltage All Inputs Except X i X2 0 5 0 8 V Vim Input High Voltage All Inputs Except X i X2 RESET 2 0 Vcc V V H2 RESET High Voltage 3 0 Vcc V VOL1 Output Low Voltage D0 D7 0 45 V lOL 2 0mA VOL2 Output Low Voltage All Other Outputs 0 45 V Iol 1 6mA Vom Output High Voltage D0 D7 2 4 V Ioh 400mA VOH2 Output High Voltage All Other...

Page 361: ... tDW Data in Setup to WR T E 150 ns two Data in Hold After WR T E ns tRD RD L E to Data Out Valid 150 ns tDF RD T E to Data Out Float 10 100 ns tMCY Matrix Cycle Time 10 7 ms With 6MHz Crystal tRV Recovery Time Between Reads and or Writes 1 MS WAVEFORMS Read Operation Data Bus Buffer Register 53 OR A X DATA VALID Write Operation Data Bus Buffer Register CS OR A V X READ CONTROLI WRITE CONTROL X DA...

Page 362: ...technologies Both numeric and alphanumeric segment displays may be used as well as simple indicators The 8279 has 16X8 display RAM which can be organized into dual 16X4 The RAM can be loaded or interrogated by the CPU Both right entry calculator and left entry typewriter display formats are possible Both read and write of the display RAM can be done with auto increment of the display RAM address P...

Page 363: ... Pins Designation Function Keyboard modes It has an active internal pullup to keep it high until a switch closure pulls it low CNTL STB For keyboard modes this line is used as a control input and stored like status on a key clo sure The line is also the strobe line that enters the data into the FIFO in the Strobed Input mode Rising Edge It has an active internal pullup to keep it high until a swit...

Page 364: ...d control status are stored in the FIFO Keys are automatically debounced with 2 key lockout or N key rollover Scanned Sensor Matrix with encoded 8x8 matrix switches or decoded 4x8 matrix switches scan tines Key status open or closed stored in RAM addressable by CPU Strobed Input Data on return lines during control line strobe is transferred to FIFO Output Modes 8 or 16 character multiplexed displa...

Page 365: ... status of the correspond ing row of sensor in the sensor matrix In this mode IRQ is high if a change in a sensor is detected Display Address Registers and Display RAM The Display Address Registers hold the address of the word currently being written or read by the CPU and the two 4 bit nibbles being displayed The read write addresses are programmed by CPU command They also can be set to auto incr...

Page 366: ...the BL flags are available for each nibble The last Clear command issued determines the code to be used as a blank This code defaults to all zeros after a reset Note that both BL flags must be set to blank a display formatted with a single 8 bit port Clear The CD bits are available in this command to clear all rows of the Display RAM to a selectable blanking coctei as follows Cp Cp Cq A I X All Ze...

Page 367: ...r matrix Although debouncing is not provided this mode has the advantage that the CPU knows how long the sensor was closed and when it was released A keyboard mode can only indicate a validated closure To make the software easier the designer should functionally group the sensors by row since this is the format in which the CPU will read them The IRQ line goes high if any sensor value change is de...

Page 368: ...e the CPU will next write to be incremented by one and the character appears in the next location With non Auto Incrementing the entry is both to the same RAM address and display position Entry to an arbitrary address in the Auto Increment mode has no undesirable side effects and the result is predictable 1st entry 2nd entry Command 10010101 3rd entry 4th entry 1 2 3 4 5 6 7 1 Display RAM Address ...

Page 369: ...that the Display RAM was unavailable because a Clear Display or Clear All command had not completed its clearing operation FjJQsta status ition In a Sensor Matrix mode a bit is s i tn word to indicate that at least one sensor au A is contained in the Sensor RAM In Special Error Mode the S E bit is showing the e pr fl jjy and serves as an indication to whether a simutfaj usfj multiple closure error...

Page 370: ...V 5 VCC 5V 10 8279 5 Symbol Parameter Min Max Unit Test Conditions V L1 Input Low Voltage for Return Lines 0 5 1 4 V V L2 Input Low Voltage for All Others 0 5 0 8 V V H1 Input High Voltage for Return Lines 2 2 V VIH2 Input High Voltage for All Others 2 0 V Vol Output Low Voltage 0 45 V Notel Vom Output High Voltage on Interrupt Line 3 5 V Note 2 VrjH2 Other Outputs 2 4 l L1 Input Current on Shift ...

Page 371: ...x Unit Uw Address Stable Before WRITE 50 ns A Address Hold Time for WRITE 20 ns tWW WRITE Pulse Width 400 250 ns tow Data Set Up Time for WR ITE 300 150 ns twD Data Hold Time for WRITE 40 ns WCY Write Cycle Time 1 1 MS Notes 1 8279 VCC 5V 5 8279 5 Vcc 5V 10 2 8279 CL 100pF 8279 5 C L 150pF Other Timings Symbol Parameter 8279 Min Max 8279 5 Min Max Unit 0W Clock Pulse Width 230 120 nsec tCY Clock P...

Page 372: ...y DATA BUS OUTPUT HIGH IMPEDANCE Y V X v high impedance V SYSTEM S ADDRESS BUS READ CONTROL s Write Operation IDC DATA BUS INPUT DATA MAY CHANGE X X DATA VALID WD X DATA MAY CHANGE SYSTEM S ADORESSBUS WRITE CONTROL Clock Input IV CY 8 82 00742A ...

Page 373: ...CY 100 kHz SOtCY 10 S XBLANK CODE I 1 CONDITIONAL WRITE TO FIFO W RLo SELECTED LATCHED BLANK CODE IS EITHER ALL O sOR ALL 1 sOR20 HEX X I RLo RL RL2 RL3 RL4 RL5 RLe RL7 RL RL RL2 RL3 RL RL5 Rlj RL7 X BLANK V co r a x r BLANK CODE C RETURN LINES ARE SAMPLED ONE AT A TIME AS SHOWN NOTE SHOWN IS ENCODED SCAN LEFT ENTRY S2 S3 ARE NOT SHOWN BUT THEY ARE SIMPLY Si DIVIDED BY 2 AND 4 8 83 00742A ...

Page 374: ...ressing DMA Handshake Provision Allows for Bus Transfers without CPU Intervention Trigger Output Pin On Chip EOS End of Sequence Message Recognition Facilitates Handling of Multi Byte Transfers The 8291 GPIB Talker Listener is a microprocessor controlled chip designed to interface microprocessors e g 8048 8080 8085 8086 to an IEEE Standard 488 Instrumentation Interface Bus It implements all of the...

Page 375: ...hake control line Indicates the avail ability and validity of infor mation on the DIO lines Symbol I O Pin No Function NRFD I O 37 Not ready for data GPIB hand shake control line Indicates the condition of readiness of de vice s connected to the bus to accept data NDAC I O 38 Not data accepted GPIB hand shake control line Indicates the condition of acceptance of data by the device s connected to t...

Page 376: ...dles communication between a microproc essor controlled device and the GPIB Its capabilities in clude data transfer handshake protocol talker listener addressing procedures device clearing and triggering service request and both serial and parallel polling schemes In most procedures it does not disturb the microprocessor unless a byte is waiting on input or a byte sent on output output buffer empt...

Page 377: ...ot Requested State I CSRS Controller Service Requested State i I CSWS Controller Synchronous Wait State I _CTRS Controller Transfer State DCAS Device Clear Active State DCIS Device Clear Idle State DTAS Device Trigger Active State DTIS Device Trigger Idle State LACS Listener Active State LAOS Listener Addressed State LIDS Listener Idle State LOOS Local State LPAS Listener Primary Addressed State L...

Page 378: ...Device Clear DC END End via L LE GET Group Execute Trigger DT GTL Go to Local RL IDY Identify L LE PP IFC Interface Clear T TE L LE C LLO Local Lockout RL MLA My Listen Address L LE RL T TE MSA My Secondary Address TE LE RL MTA My Talk Address T TE L LE OSA Other Secondary Address TE OTA Other Talk Address T TE PCG Primary Command Group TE LE PP TPPC Parallel Poll Configure PP t PPD Parallel Poll ...

Page 379: ...ess via C MTA or MTA My Talk Address via C OSA Other Secondary Address via C OTA Other Talk Address via C PCG Primary Command Group via C PPC Parallel Poll Configure via C PPDJ Parallel Poll Disable via C PPE Parallel Poll Enable via C PPRn Parallel Pol Response N PP PPU Parallel Poll Unconfigure via C REN Remote Enable C RFD Ready for Data AH RQS Request Service T TE SDC Selected Device Clear via...

Page 380: ...Bl INTERRUPT MASK 1 DMAO DMAI SPASC LLOC REMC ADSC INTERRUPT MASK 2 S8 rsv S6 S5 S4 S3 S2 SI SERIAL POLL MODE TO LO ADM1 ADMO ADDRESS MODE CNT2 CNT1 CNTO COM4 COM3 COM2 COM1 COM0 AUX MODE ARS DT DL AD5 AD4 AD3 AD2 AD1 ADDRESS 0 1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 ECO ADDRESS 1 EOS Data Registers DI7 DI6 DI5 DI4 DI3 DI2 DM DIO DATA IN REGISTER OR D07 DO6 D05 D04 D03 D02 DOI DOO DATA OUT REGISTER 0W The d...

Page 381: ...sters are then cleared upon being read or when a local pon power on message is executed If an event occurs while one of the Interrupt Status registers is being read the event is typically held until after its register is cleared and then placed in the register The mnemonics for each of the bits in these registers and a brief description of their respective functions appears in Table 4 This table a...

Page 382: ...vailable in the CPT register for validation This interrupt will only occur if Mode 3 addressing is in effect Refer to the section on addressing In Mode 2 secondary addresses will be recognized on the 8291 They will be ignored in Mode 1 The CPT interrupt bit flags the occurrence of an unde fined command and of all secondary commands follow ing an undefined command The Command pass through feature i...

Page 383: ...oll is conducted and the controller in charge reads the status byte the SRQS bit is cleared The SRQ line is tied to this bit so that a request for service is terminated when the 8291 s status byte is read The rsv bit of the Serial Poll Mode Register must then be cleared by the microprocessor TO LO ADM1 ADMO ADDRESS MODE 4W ARS DT DL AD5 AD4 AD3 AD2 AD1 ADDRESS 0 1 6W ADDRESS 1 7R The Address Mode ...

Page 384: ...th the talker and the listener should be disabled at the Minor address As an example of how the Address 0 1 Register might be used consider an example where two primary addresses are needed in the device The Major primary address will be selectable only as a talker and the Minor primary address will be selectable only as a listener This configuration of the 8291 is formed by the following sequence...

Page 385: ...AIDS TIDS LIDS NPRS LOCS and PPIS The 0000 pon is an immediate execute command a pon pulse It is also used to release the initialize state generated by either an external reset pulse or the 0010 Chip Reset command Chip Reset Initialize This command has the same effect as a pulse applied to the Reset pin Refer to the section on Reset Procedure Finish Handshake This command finishes a handshake that...

Page 386: ...ll be set in the Interrupt Status 1 Register A3 Output EOI on EOS Sent Any occurrence of data in the Data Out Register matching the EOS Register causes the EOI line to be sent true along with the data A4 EOS Binary Compare Setting this bit causes the EOS Register to function as a full 8 bit word When it is not set the EOS Register is a 7 bit word for ASCII characters If Ao A1 1 a special continuou...

Page 387: ...It then sends the appropriate Ipe local message to the 8291 Finally the microprocessor sends VSCMD and the handshake is released As defined in IEEE Standard 488 End of Sequence EOS Register EC7 EC6 EC5 EC4 EC3 EC2 EC1 ECO EOS REGISTER The EOS Register and its features offer an alternative to the Send EOI auxiliary command A seven or eight bit byte ASCII or binary may be placed in the register to f...

Page 388: ...generated indicating that the Data Out Register is empty and DMA REQ is asserted 2 DMA ACK is asserted by the 8257 and DMA REQ is reset 3 WR is driven by the 8257 and a byte is transferred from the MCS bus into the Data Out Register 4 The 8291 sends DAV true on the GPIB and proceeds with the Source Handshake protocol It should be noted that each time the device is addressed the Address Status Regi...

Page 389: ...ce Vcc Supply Current 180 mA Ta 0 C A C CHARACTERISTICS Vcc 5V 10 Commercial Ta 0 C to 70 Symbol Parameter Min Max Unit tAR Address Stable Before READ nsecl 1 tRA Address Hold After READ nsecl 1 250 tRR READ width nsec 2 tAD Address Stable to Data Valid 250 nsecl 1 tRD READ to Data Valid 100 nsecl 2 tRDF Data Float After READ 60l 2 l nsec tAW Address Stable Before WRITE nsecl 1 tWA Address Hold Af...

Page 390: ... DATA OUT X r V VALID DATA WRITE DMA ZX DATA BUS DATA IN X X aw DATA MAY CHANGE tDw tWA t RV A WD V VALID DATA if DATA MAY CHANGE NOTES 1 t Rv IS THE TIME BETWEEN READ OR WRITE OPERATIONS WITH THE CHIP SELECTED CHIP RECOVERY TIME J K V_ 8 100 00229A ...

Page 391: ...C DAVJ to NDACf 350 nsec AH CACS TNDDV1 NDACt to DAVt 300 nsec SH STRS TNRDV2 NRFD1 to DAV1 300 nsec SH T1 True TNDDR1 NDACt to DREQI 350 nsec SH TDVDR3 DAVl to DREQt 350 nsec AH LACS ATN 2 4V TDVND2 C DAVt to NDACJ 350 nsec AH LACS TDVNR1 C DAVt to NRFDt 350 nsec AH LACS rdy True TRDNR3 RD to NRFDt 500 nsec AH LACS TWRDI5 WR to DlO Valid 200 nsec SH TACS RS 0 4V TWRDV2 WRt to DAW 760 nsec NRFD 2 ...

Page 392: ...state are indicated D All remote multiline messages decoded are condi tioned by ACDS The multiplication by ACDS is not drawn to simplify the diagrams E The symbol e indicates 1 When event X occurs the function will return to state S 2 X overrides any other transition condition in the function Statement 2 simplifies the diagram avoiding the explicit use of X to condition all transitions from S to o...

Page 393: ...8291 ton MTA MODE 1 MSA TPAS MODE 1 Figure A 1 8291 State Diagrams Continued next page 8 103 00229A ...

Page 394: ...e values specified by an upper case T indicate the minimum time that a function must remain in a state before exiting t If three state drivers are used on the DIO DAV and EOI lines Ti may be 1 1100ns 2 Or 700ns if it is known that within the controller ATN is driven by a three state driver 3 Or 500ns for all subsequent bytes following the first sent after each false transition of ATN the first byt...

Page 395: ...8291 Appendix C THE THREE WIRE HANDSHAKE X X ALL READY DATA TRANSFER BEGINS NONE READY TTT SOME ACC TTTT SOME READY I ALL READY ALL ACC TRANSFER ENDS Figure C 1 3 Wire Handshake Timing 8 105 00229A ...

Page 396: ...IL SET DAV HIGH ALL ACCEPTORS HAVE ACCEPTED IT DATA IS NOT TO BE CONSIDERED VALID AFTER THIS TIME J SET NRFD AND NDAC LOW NO S READY TO ACCEPT DATA SET NRFD HIGH ACCEPT DATA BYTE SET NRFD LOW SET NDAC HIGH FLOW DIAGRAM OUTLINES SEQUENCE OF EVENTS DURING TRANSFER OF DATA BYTE MORE THAN ONE LISTENER AT A TIME CAN ACCEPT DATA BECAUSE OF LOGICAL AND CONNECTION OF NRFD AND NDAC LINES Figure C 2 Handsha...

Page 397: ...ACE BUS SIGNAL LINES 2 REMOTE INTERFACE MESSAGES TO AND FROM INTERFACE FUNCTIONS 3 DEVICE DEPENDENT MESSAGES TO AND FROM DEVICE FUNCTIONS 4 STATE LINKAGES BETWEEN INTERFACE FUNCTIONS 5 LOCAL MESSAGES BETWEEN DEVICE FUNCTIONS AND INTERFACE FUNCTIONS MESSAGES TO INTERFACE FUNCTIONS ARE DEFINED MESSAGES FROM INTERFACE FUNCTIONS EXIST ACCORDING TO THE DESIGNER S CHOICE 6 CONTROL MESSAGES 8292 ONLY Fig...

Page 398: ...Interface Talker Listener Controller The 8292 GPIB CONTROLLER is a microprocessor controlled chip designed to connect with the 8291 GPIB TALKER LISTENER to implement the full IEEE Standard 488 controller function including transfer control protocol The 8292 is a pre programmed UPI 41AlM PIN CONFIGURATION 8291 8292 SYSTEM DIAGRAM L MICROPROCESSOR SYSTEM BUS DMA 1 CONTROLLER I I OPTIONAL 8291 GPIB T...

Page 399: ...fer Not Full Used to in terrupt the central processor while the input buffer of the 8292 is empty This feature is enabled and disabled by the interrupt mask register ATNO O 29 SRQ 21 REN O 38 TCI O 32 SPI O 33 CLTH O 27 IFCR I 1 COUNT I 39 X1t X2 I 2 3 SYNC 11 VCC P S 40 Vss P S 7 20 Attention Out Controls the ATN control line of the bus through ex ternal logic for tcs take control synchronously p...

Page 400: ...ated with data transfer Also by using the DMA interface two or more DEUs may be operated in parallel to achieve effective system conversion rates which are virtually any multiple of 80 bytes second The 8294 also has a 7 bit TTL compatible output port for user specified functions Because the 8294 implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer applic...

Page 401: ... Furthermore it provides internal buffering of up to 40 characters and contains a 7x 7 matrix character generator accommodating 64 ASCII characters PIN CONFIGURATION PIN NAMES BLOCK DIAGRAM PIN NAME FUNCTION D0 D7 DATA BUS RD WR READ WRITE STROBES CS CHIP SELECT RESET RESET INPUT X1 X2 FREQUENCY REFERENCE INPUTS SYNC HIGH FREQUENCY OUTPUT MOT PFM MAIN PAPER FEED MOTOR DRIVES DRO DACK DMA REQUEST A...

Page 402: ...nction as either in puts or outputs under software control I O can be expanded with the 8243 device which is directly compatible and has 16 I O lines An 8 bit programmable timer counter is included in the UPI device for generating timing sequences or counting external inputs Additional UPI features include single 5V supply low power standby mode in the 8041A single step mode for debug in the 8741 ...

Page 403: ...V STS A single byte single cycle instruction Bits 4 7 of the accumulator are moved to bits 4 7 of the status register Bits 0 3 of the status register are not affected MOV STS A Op Code 90H 10 0 3 RD and WR are edge triggered IBF OBF F and INT change internally after the trailing edge of RD or WR r FLAGS AFFECTED Y V P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a mas...

Page 404: ...PT CAPABILITY EN FLAGS Op Code 0F5H 1 D7 D P26 and P27 are port pins or DMA handshake pins for use with a DMA controller These pins default to port pins on Reset If the EN DMA instruction has been executed P26 becomes the DRQ DMA ReQuest pin A 1 written to P26 causes a DMA request DRQ is activated DRQ is deactivated by DACK RD DACK WR or execution of the EN DMA instruction If EN DMA has been execu...

Page 405: ...sed during PROM programming and verification Single step input used in the 8741A in conjunction with the SYNC output to step the program through each instruction 5V power supply pin 5V during normal operation Programming supply pin during PROM programming Low power standby pin in ROM version Circuit ground potential ACCUMULATOR ADD A Rr Add register to A ADD A Rr Add data memory to A ADD A data Ad...

Page 406: ... addr Jump to subroutine 2 2 JNTO addr Jump on T0 2 2 RET Return 1 2 JT1 addr Jump on T1 1 2 2 RETR Return and restore status 1 2 JNT1 addr Jump on T1 0 2 2 FLAGS JFO addr Jump on F0 Flag 1 2 2 JF1 addr Jump on F1 Flag 1 2 2 CLRC Clear Carry 1 1 JTF addr Jump on Timer Flag 1 Clear Flag 2 2 CPLC Complement Carry 1 1 JNIBFaddr Jump on IBF Flag 2 2 CLRFO Clear Flag 1 1 JOBF addr Jump on OBF Flag 1 2 ...

Page 407: ... Low Voltage All Other Outputs Except Prog 0 45 V l 0L 1 6 mA VOL3 Output Low Voltage Prog 0 45 V l OL 1 0 mA VOH1 Output High Voltage D D7 2 4 V l 0H 400 MA VOH2 Output High Voltage All Other Outputs 2 4 V l 0H 50yA IlL Input Leakage Current T T1f RD WR CS A EA 10 ma Vss V N Vcc loz Output Leakage Current D D7 High Z State 10 ma Vss 0 45 V N Vcc Ilm Low Input Load Current P10P17 P20p27 0 5 mA V L...

Page 408: ...put Data Hold Time 110 ns tpp PROG Pulse Width 1400 ns PS Input Data Setup Time 700 ns WAVEFORMS PORT 2 J V J V EXPANDER PORT OUTPUT EXPANDER PORT INPUT IX ZX A C CHARACTERISTICS DMA TA 0 C to70 C VCC 5V 10 Y PORT 2 3 DATA Y PORT CONTROL OUTPUT DATA j H rc c V g T Symbol Parameter Min Max Unit Test Conditions Ucc DAC to WR or RD ns tcAC RD or WR to DACK ns l ACD DACK to Data Valid 225 ns CL 150pF ...

Page 409: ...D7 D Outputs R L 2 2k to Vss 4 3k to VCc CL 100 pF WAVEFORMS 1 READ OPERATION DATA BUS BUFFER REGISTER 55 OR A IX X DATA VALID READ CONTROL 2 WRITE OPERATION DATA BUS BUFFER REGISTER BORA L x IWRITE CONTROL V DATA VALID 8 119 001 88A ...

Page 410: ... 2 Insert 8741 A in programming socket 3 TEST OV select program mode 4 EA 25V activate program mode 5 Address applied to BUS and P20 1 6 RESET 5V latch address 7 Data applied to BUS 8 VD 25V programming power 9 PROG OV followed by one 50 ms pulse to 25V 10 VDD 5V 11 TEST 5V verify mode 12 Read and verify data on BUS 13 TESTO OV 14 RESET OV and repeat from step 5 15 Programmer should be at conditio...

Page 411: ...lamp tubes dur ing erasure Some lamps have a filter on their tubes which should be removed before erasure A C TIMING SPECIFICATION FOR PROGRAMMING TA 25 C 5 C Vcc 5V 5 VDD 25V 1V Symbol Parameter Min Max Unit Test Conditions tAW Address Setup Time to RESET t 4tcy tWA Address Hold Time After RESET i 4tcy tDW Data in Setup Time to PROG l 4tcy tWD Data in Hold Time After PROG 1 4tcy tPH RESET Hold Ti...

Page 412: ...DR V UB UB7 f 0 7 VALID A PROGRAMMED VALID t A VALID T VALID Al izzzx P20 Pl ADDRESS y ADDRESS 8 9 VALID A VDDH tWT DO 7 i j NEXT ADDRESS A Verify Mode ROM EPROM VERIFY MODE ROM EPROM J V ADDRESS J DATA OUT _ NEXT y NEXT DATA 0 7 VALID Al VALID f ADDRESS hi OUT VALID 7 ADDRESS 8 9 VALID X NEXT ADDRESS VALID 8 122 00188A ...

Page 413: ...Chapter 9 SUPPORT PRODUCTS ...

Page 414: ...t System 9 1 Model 230 Intellec Series 11 Microcomputer Development System 9 5 Intellec PROMPT 48 MCS 48 Microcomputer Design Aid 9 9 ICE 49 MCS 48 In Circuit Emulator 9 15 EM1 8021 Emulation Board 9 20 EM2 8022 Emulation Board 9 23 UPP 103 Universal PROM Programmer 9 26 ...

Page 415: ...ocomputer Development System is a complete microcomputer development system integrated into one compact package It includes a CPU with 32K bytes of RAM memory 4K bytes of ROM memory a 2000 character CRT detachable full ASCII keyboard with cursor controls and upper lower case capability and a 250K byte floppy diskette drive Powerful ISIS II Diskette Operating System software allows the Model 220 to...

Page 416: ...annels on the IPB itself Each serial channel is RS232 compatible and is capable of running asynchronously from 1 10 to 9600 baud or synchronously from 150 to 56K baud Both may be connected to a user defined data set or data terminal One channel contains current loop adapters Both channels are implemented using Intel s 8251 USART They can be programmatically selected to perform a variety of I O fun...

Page 417: ...eight interrupt switches and indicators the front panel circuit board is attached directly to the IPB allowing the eight interrupt switches to connect to the primary 8259 as well as to the Intellec Series II bus MULTIBUS Capability All Intellec Series II models implement the industry standard MULTIBUS MULTIBUS enables several bus masters such as CPU and DMA devices to share the bus and memory by o...

Page 418: ...Series II Installation and Service Manual SUPPLIED 9800306 ISIS II System User s Guide SUPPLIED 9800556 Intellec Series II Hardware Reference Man ual SUPPLIED 9800555 Intellec Series II Hardware Interface Manual SUPPLIED 9800301 8080 8085 Assembly Language Program ming Manual SUPPLIED 9800605 Intellec Series II System Monitor Source Listing SUPPLIED 9800554 Intellec Series II Schematic Drawing SUP...

Page 419: ...ies II Microcomputer Development System is a complete center for the development of microcomputer based products It includes a CPU 64K bytes of RAM 4K bytes of ROM memory a 2000 character CRT a detachable full ASCII keyboard and dual double density diskette drives providing over 1 million bytes of on line data storage Powerful ISIS II Diskette Operating System software allows the Model 230 to be u...

Page 420: ...he slave CPU card communicates with the IPB over an 8 bit bidirec tional data bus Memory and Control Cards In addition 32K bytes of RAM bringing the total to 64K bytes is located on a separate card in the main cardcage Fabricated from Intel s 16K RAMs the board also contains all necessary address decoding and refresh logic Two additional boards in the cardcage are used to control the two double de...

Page 421: ...similar functions to the UPI 41 on the PIO board in the Model 210 It provides interface for other standard Intellec peripherals including a printer high speed paper tape reader high speed paper tape punch and universal PROM programmer Communication between the IPB and IOC is maintained over a separate 8 bit bidirectional data bus Connectors for the four devices named above as well as the two seria...

Page 422: ... Equipment Supplied Model 230 chassis Integrated processor board IPB I O controller board IOC 32K RAM board CRT and keyboard Double density floppy disk controller 2 boards Dual drive floppy disk chassis and cables 2 floppy disk drives 512K byte capacity each ROM resident system monitor ISIS II system diskette with MCS 80 MCS 85 macroassembler Reference Manuals 9800558 A Guide to Microcomputer Deve...

Page 423: ...ystem power requirement Integral keyboard and displays no tele typewriter or CRT terminal required Extensive PROMPT 48 monitor allowing system I O bus and memory expansion Includes comprehensive design library The Intellec Prompt 48 MCS 48 Microcomputer Design Aid is a low cost fully assembled design aid for the revolu tionary 8748 single component microcomputer PROMPT 48 simplifies the programmin...

Page 424: ...ution socket The execution socket pro cessor runs either monitor or user programs System Monitor The system reset command initializes the PROMPT system and enters the monitor The monitor interrupt command exits a user program gracefully preserving system status and entering the monitor The user inter rupt command causes an interrupt only if the PROMPT system is running a user program A comprehensi...

Page 425: ...ple EPROM PROMPT RAM or external program memory and a variety of input output options may be selected Allows any or all of the eight breakpoints to be set and cleared Clears portions of register data or program memory Dumps register data or program memory to PROMPT S serial channel for example a teletypewriter paper tape punch Enters reads register data or program memory from PROMPT S serial chann...

Page 426: ...cillator and clock driver and circuitry for interrupts and resets Extra cir cuitry is in the 8048 ROM processor to allow low power standby operation The 64 x 8 RAM data memory can be independently powered Compatibility For systems requiring additional com patibility the MCS 48 can be expanded with the new 8243 I O expander 8155 I O and 256 byte RAM 8755 I O and 2K byte EPROM or 8355 I O and 2K ROM...

Page 427: ...ial I O expander 8243 or standard peripherals Reset and Interrupts Reset initializes the PROMPT system and enters the monitor Monitor Interrupt exits a user program gracefully preserving system status and entering the monitor User Interrupt causes an interrupt only if the PROMPT system is running a user program The processor traps to location 3 16 The MCS 48 timer event counter is not used by the ...

Page 428: ... Depth 17 in 43 2 cm max Weight 21 lb 9 6 kg Electrical Characteristics Pe er Requirements either 115 or 230V AC 10 may be switch selected on the mainframe 1 8 amps max current at 125 V AC Frequency 47 63 Hz Environmental Characteristics Operating Temperature 0 C to 40 C Non Operating Temperature 20 C to 65 C Note R D or P is register data or program Software Drivers Panel Keyboard In KBIN KDBIN P...

Page 429: ...th an MCS 48 system through a cable terminating in an MCS 48 pin compatible plug which replaces the MCS 48 device in the sytem With the ICE 49 plug in place the designer has the capability to execute the system in real time while collecting up to 255 instruction cycles of real time trace data In addition he can single step the system program to monitor more closely the program logic during executi...

Page 430: ...tellec system resources can be accessed to replace prototype mem ory Hardware designs can be tested using the system software to drive the final product Thus the system in tegration phase which can be costly when attempting to mesh completed hardware and software products becomes a convenient two way debug tool when begun early in the design cycle Real Time Trace The ICE 49 module captures trace i...

Page 431: ...9 8039 emulation character istics The 8048 8748 provides the 8748 8648 8035 8021 emulation characteristics The ICE 49 module uses an Intel 8080 to communicate with the Intellec host pro cessor via a common memory space The 8080 also con trols an internal ICE 49 bus for intramodule communica tion ICE 49 hardware consists of two PC boards the controller board and the emulator board all of which resi...

Page 432: ... contents of memory register output port or flag Sets or alters break points and display registers Defines memory status Establishes mode of display for output data Establishes mode of display input data Table 2 ICE 49 Interrogation Commands Command Operation Load Fetches user symbol table and object code from input device Save Sends user symbol table and object code to output device Define Enters...

Page 433: ... condensation Reference Manuals 9800632 ICE 49 Operator s Manual SUPPLIED Reference manuals are shipped with each product only if designated SUPPLIED see above Manuals may be ordered from any Intel sales representative distributor office or from Intel Literature Department 3065 Bowers Avenue Santa Clara California 95051 ORDERING INFORMATION Part Number MDS 49 ICE MDSi 498 Description 8049 8048 803...

Page 434: ... mask programmable ROM program memory and 64x8 RAM data memory The EM1 is controlled by an Intel 8748 with 1 K of EPROM program memory and a 64 byte data memory The EPROM can be programmed and erased repeatedly during hardware and software development The EM1 has several ancillary circuits that perform the following functions which are specific to the 8021 Zero crossing detector Crystal controlled...

Page 435: ...signal on a positive crossing and a low level signal on a negative crossing of zero to the T1 input of the 8748 Reset Buffer The 8021 resets on a logic HIGH level signal However the 8748 resets on a logic LOW level thus an inverter is provided on the MDS EM1 to make the two chips com patible Optional Pull Ups Resistors are provided to simulate the optional pull up resistors on T1 input and port of...

Page 436: ... with 8021 EM1 Operator s Manual System Clock Crystal controlled 3 0 MHz on board or user supplied TTL external clock hardware jumper selectable Physical Characteristics Width 7 0 in 17 78 cm Height 4 0 in 10 16 cm Depth 0 75 in 1 91 cm Weight 1 0 lb 0 45 kg Electrical Characteristics DC Power VCC 5V 5 Ice 300 mA max Environmental Characteristics Operating Temperature 0 C to 55 C Operating Humidit...

Page 437: ...vides the user a full EPROM functional and electrical equivalent of the 8022 single compo nent 8 bit microcomputer The IEM2 emulator board consists of an Intel 8022 emulator chip and an Intel 8755A providing the EM2 emulator board with a 2Kx8 EPROM program memory which can be programmed and erased repeatedly during hardware and software development The 8022E emulator chip is a modified version of ...

Page 438: ...uc tions JT0 and JNT0 Initiates an inter rupt following a low level input if inter rupt is enabled Interrupt is disabled after a reset T1 19 Input pin testable using the JT1 and JNT1 conditional transfer instructions Can be designated the timer event counter input using the STRT CNT in struction Also serves as the zero cross detection input to allow zero crossover sensing of slowly moving AC input...

Page 439: ...xposure to ultraviolet light which has a wavelength of 2537A The integrated dose UV intensity multiplied by exposure time for erasure should be a minimum of 15W sec cm The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12 000p W em2 power rating Place the 8755A within one inch of the lamp during erasure Some lamps include a filter which should be r...

Page 440: ...ate programming operations using several PROM types The UPP 103 Universal PROM Programmer is an Intellec system peripheral capable of programming and verifying the following Intel programmable ROMs PROMs 1702A 2704 2708 2716 3601 8702A 8704 and 8708 In addition the UPP 103 programs the PROM memory portions of the 8748 microcomputer and the 8755 PROM and I O chip Program ming and verification opera...

Page 441: ...rsonalized PROM pro gramming routines because it contains the program ming algorithms for all Intel PROM families Optional Versions There are two versions of the UPM one that runs under the Intellec system monitor paper tape system and one that runs under ISIS II the Intellec diskette operat ing system diskette based system The paper tape ver sion is included with the Universal PROM Programmer The...

Page 442: ......

Page 443: ...Appendices PACKAGING INFORMATION AND ORDERING INFORMATION ...

Page 444: ...APPENDICES Packaging Information A1 1 Ordering Information A2 1 ...

Page 445: ...40 40 40 I O Expander 8243 D P 24 Standard ROMs 8308 2316E D P C D P 24 24 Standard EPROM 2708 2716 B D B 24 24 Standard RAMs 2111A 4 2101A 4 5101 D P D P D P 18 22 24 Standard I O 8212 8255A 8251 D P D P D P 24 40 28 Standard Peripherals 8205 8214 8216 8226 8253 8259 8278 8279 D P D P D P D P D P D P D P D P 16 24 16 16 24 28 40 40 Universal Peripheral Interface 8041 8741 D P C 40 40 B Black Cera...

Page 446: ...794 090 2 286 015 MIN 0 381 020 0 508 016 0 406 010 TYP 0 254 zfc i 350 h 8 890 J 16 LEAD HERMETIC DUAL IN LINE PACKAGE TYPE D 18 LEAD PLASTIC DUAL IN LINE PACKAGE TYPE P 200 5 080 MAX PLANE 125 3 1751 MIN 255 6 467 245 6 223 325 MAX 8 255 015 MIN 0 381 010 TYP 0 254 zfe 110 2 794 090 2 286 I 350 I U 8 890 J 350 i 890 REF A1 2 ...

Page 447: ...X 1 8 255 1 010 TYP 0 254 1 15 376 19 525 REF 22 LEAID PLASTIC DUAL IN LINE PACKAGE TYPE P 015 MIN 0 381 020 0 508 016 0 406 010 TYP 0 254 425 MAX 10 795 h Jkii I 4S0 I It 11 430 22 LEAD HERMETIC DUAL IN LINE PACKAGE TYPE D 200 5 080 MAX iP 110 2 794 _ 425 MAX C MAX 110 795 f_ 015MIN 0 381 JU 020 0 508 016 0 406 010 TYP 0 254 475 12 065 REF A1 3 ...

Page 448: ...N LINE PACKAGE TYPE P 010 TYP 0 254 625 MAX 15 8751 fflU 110 2 794 090 2 2861 650 j U 16 510 24 LEAD HERMETIC DUAL IN LINE PACKAGE TYPE D 1 285 32 639 28 LEAD PLASTIC DUAL IN LINE PACKAGE TYPE P 625 h MAX 15 875 125 3 175 J MIN 110 2 794 T090 2 2861 010 TYP 0 254 L 650 116 510 REF A1 4 ...

Page 449: ...s and millimeters 28 LEAD HERMETIC DUAL IN LINE PACKAGE TYPE D 40 LEAD PLASTIC DUAL IN LINE PACKAGE TYPE P 200 5 080 MAX 625 MAX 15 875 010 TYP 0 254 I I 650 I 16 S10 J 650 16 510 REF 40 LEAD HERMETIC DUAL IN LINE PACKAGE TYPE D 2 080 52 832 A1 5 ...

Page 450: ...AGE TYPE C 1 215 30 861 N 145 MAX OKilAU 3683 070 1 778 I I 022 0 558 i 625 j I ct nram L 15 875 _ T 010 TYP 020 MIN 0 254 1 V10 1 558 015 0 381 40 LEAD HERMETIC DUAL INLINE PACKAGE TYPE C 2 020 51 308 2 PIN 1 1 980 50 29 L 020 MIN il 0 508 li_J 22 10 558 015 0 381 010 TYP 0 254 I 625 I 15 875 A1 6 ...

Page 451: ...metic package Type D military temperature range MIL STD 883 Level C processing MC8080A B 8080A Microprocessor hermetic package Type C military temperature range MIL STD 883 Level B processing Kits boards and systems may be ordered using the part number designations in this catalog The latest Intel OEM price book should be consulted for availability of various options These may be obtained from you...

Page 452: ...ation may be sent on Intel Microcomputer Development System Floppy Disk When using this input medium the floppy disk file name should be indicated in the Customer Part Number Section below The type of floppy disk sent should also be indicated by checking one of the appropriate boxes Single Density D Double Density CUSTOMER PART NUMBER Customer P N Please Fill in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 453: ...and the customer part number Z Z The customer part number is limited to a maximum of 9 digits or spaces P8048 XXYY WWWW Z Z 1 P8048 MARKING EXAMPLE FLOPPY DISK Programming information may be sent on Intel Microcomputer Development System Floppy Disk When using this input medium the floppy disk file name should be indicated in the Customer Part Number Section below The type of floppy disk sent shou...

Page 454: ...the 4 digit Intel pattern number WWWW a date code XXYY and the customer part number Z Z The customer part number is limited to a maximum of 9 digits or spaces I P8021 XXYY WWWW Z Z P8021 MARKING EXAMPLE CUSTOMER PART NUMBER Customer P N Please Fill in I I L J I L Intel Pattern Number Please Do Not Use I I L I O Mask Options Specify the desired connection for each I O line on Port and for the T1 in...

Page 455: ... digit Intel pattern number WWWW a date code XXYY and the customer part number Z Z The customer part number is limited to a maximum of 9 digits or spaces I P8022 XXYY WWWW Z Z P8022 MARKING EXAMPLE CUSTOMER PART NUMBER Customer P N Please Fill in L_l I I I I I Intel Pattern Number Please Do Not Use I I I I I I I L I O Mask Options Specify the desired connection for each I O line on Port and for th...

Page 456: ...er Card Master Device Intel Microcomputer Intellec Hex Intellec Hex Same Density and Development System Pin Compatible Single or Double BPNF PN to Device which Density Disk is to be Pro Hex grammed A1 Logic Levels All data field for Intel s EPROMs PROMs ROMs are positive logic The only exceptions are the 4001 and 4308 ROMs which use negative logic For the 4001 4308 an 0 is a high output and a 1 is...

Page 457: ...ield The high order digit is in frame 1 The maximum number of data bytes in a record is 255 FF in hexadecimal An end of file record contains two ASCII zeros in this field 3 LOAD ADDRESS FIELD Frames 3 6 The four ASCII hexadecimal digits in frames 3 6 give the address at which the data is loaded The high order digit is in frame 3 the lower order digit in frame 6 The first data byte is stored in the...

Page 458: ...rubout any erroneous character s The character may be used to rubout an entire line up to the previous carriage return 4 Spaces are allowed only between separate word fields 5 After each 72 characters a carriage return followed by a line feed should be punched to allow a print out of the tape 6 Comments must be placed only between the tape leader and the start of the first data field C Computer Pu...

Page 459: ...ough the load address for the beginning record need not be 0000 each subsequent load address should be 10h 16 decimals greater than the last 8 9 Record type A 2 digit code in this field speci fies the type of this record The high order digit of this code is located in Column 8 Currently all data records are type 0 End of file records will be type 1 they are dis tinguished by a zero RECORD LENGTH f...

Page 460: ...unch a 2 diqit decimal i imber to indicate truth table number The first truth tabic will be 00 second 01 third 02 etc Title Card Format For a N words X 4 bit organization only cards 2 and those following should be punched as shown Each card specifies the 4 bit output of 14 words DECIMAL WORD ADDRESS BEGINNING EACH CARD I MSB 14 DATA FIELDS t r t liUNh f f f f H F F F Iti tr f H H DECIMAL NUMBER IN...

Page 461: ... i 1 1 U 6 6 i i IP llll I II II III II II III III II II II H I S I 1 1 f I P t 1 1 1 H I I 1 1 1 I f m 1 1 I f 1 1 1 1 1 I I 1 1 f I I I i S I M I i i I I S I i I I I i E I i II 8 S i il i nnu niu i v HHnijj 5 i nlst ii I M liinii H Column Data 1 5 Punch the 5 digit decimal equivalent of the binary coded location which begins each card The address Is right justified i e 00000 00008 000 1 6 etc 6 ...

Page 462: ...OG Monterey Calif Prometrics Chicago III and Turner Designs Mt View Calif The individual manufacturers should be consulted for detailed product descriptions Also shown in the table are typical erase times for various combinations of Intel PROMs and lamp intensities Table IV Model Power Rating Minimum Erase Time for Indicated Dosage Without a Filter Over the Bulb 6 W sec 1702A 4702A 15 W sec 2708 8...

Page 463: ...Normandale Avenue Suite 422 Bloomington 55437 Tel 612 835 6722 TWX 910 576 2867 tDytek North 1821 University Ave Room 163N St Paul 55104 Tel 612 645 5816 MISSOURI Technical Representatives Inc 320 Brookes Drive Suite 104 Hazelwood 63042 Tel 314 731 5200 TWX 910 762 0618 NEW JERSEY Intel Corp 1 Metroplaza Office Bldg 505 Thornall St Edison 08817 Tel 201 494 5040 TWX 710 480 6238 NEW MEXICO BFA Corp...

Page 464: ...ics 6700 I 85 Access Road 11 Norcross 30071 Tel 404 448 0800 ILLINOIS fCramer Chicago 1911 So BusseRd Mt Prospect 60056 Tel 312 593 8230 fHamilton Avnet Electronics 3901 No 25th Ave Schiller Park 60176 Tel 317 849 7300 Pioneer Chicago 1551 Carmen Drive Elk Grove Village 60006 Tel 312 437 9680 INDIANA fPioneer lndiana 6408 Castleplace Drive Indianapolis 46250 Tel 317 849 7300 Sheridan Sales 8790 Pu...

Page 465: ...oad Horsham 19044 Tel 215 674 4000 TWX 510 665 6778 TENNESSEE fSheridan Sales Co 6900 Office Park Circle Knoxville 37919 Tel 615 588 5836 TEXAS Component Specialties Inc 8330 Burnett Road Suite 101 Austin 78758 Tel 512 459 3308 fCramer Electronics 13740 Midway Road Dallas 75240 Tel 214 661 9300 fHamilton Avnet Electronics 4445 Sigma Road Dallas 75240 Tel 214 661 9300 fHamilton Avnet Electronics 39...

Page 466: ...F1 CPL F1 BRANCH JMP addr JMPP A DJNZ R r addr JC addr JNC addr JZ addr JNZ addr JT0 addr JNTO addr JT1 aadr JNT1 addr JFO addr JF1 addr JTFaddr JNI addr JBO addr JB1 addr JB2 addr JB3 addr JB4 addr JB5 addr JB6 addr JB7addr TIMER MOV A T MOV T A STRT T STRT CNT STOP TCNT EN TCNTI DIS TCNTI 1 c 10 11 E 97 A7 85 95 A5 B5 t4 B3 E F6 E6 C6 96 36 26 56 46 B6 76 16 86 12 32 52 72 92 B2 D2 F2 42 62 55 4...

Page 467: ...C 3C 9C 8C P5 OD 3D 9D 8D P6 OE 3E 9E 8E P7 OF 3F 9F 8F TABLE 3 BRANCH Page JMP CALL 04 14 1 24 34 2 44 54 3 64 74 4 84 94 5 A4 B4 6 C4 D4 7 E4 F4 Page 256 bytes MCS 48 DATA TRANSFER INSTRUCTIONS EXPANDER I O PORTS PROGRAM MEMORY l dtti MOVO ANLO ORLO a DATA MEMORY WORKING REG a ADO MOV MOVP M0VP3 ANL ORl XRL MOV ADO ANL ORL XRL XCH 7 1Z n MOV ADD ANL ORL XRL XCH XCHD ik ACCUMULATOR TIMER COUNTER ...

Page 468: ...NOTES ...

Page 469: ...6364 schmitten 2 Tol I a212543 TELEX 416335 HONG KONQ n i nd S Co JB F Wing ofl Cenlar Hong Kong e 5 i50266 TELEX 747841 Sehmc Hi INDIA Mirra Eleclrofiics Imemationai i s JM 1MA Sr nrir agF Hyderabad J MfJ r Mi Mi zC SC HVOERBAD SCANDINAVIA L uiil niPti Intel Suandinavia A 5 P O BOX 1SS N 2O40 Kiofta Norway Tel 47 Z 98 1CT TFLEX 18014 Intel Scandinavia A 8 lox T Scoli rikitja 3 i Hfilsink Finlpnd ...

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