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Display Subsystem Use Cases and Tips
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Length of the line in video mode in Nb of byte clock cycles (TxByteClkHS):
TL = FHSB/FVPP × (DIS DIS PPL + DISPC_HBP)
TL1f = (BPP/(8 × NDL)) × (DIS DIS PPL +DISPC_HBP)
(29)
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Blanking periods (HBP + HFP) in DSI are calculated based on the following formula:
(DIS DIS PPL + DISPC_HFP) × Fppi = (HS + HBP + ((WC + 6)/NDL) +HFP) ×
Fvp
HBP + HFP = (TVPP/THSB) × (DIS DIS PPL + DISPC_HBP – (HS + (WC +
6)/NDL))
HBPplusHFP = (FHSB/FVPP) × (DIS DIS PPL + DISPC_HBP) – (HS + WC +
6)/NDL)
HBPplusHFPf = ((FHSB/FVPP) × (DIS DIS PPL + DISPC_HBP)) – ((HS + WC +
6)/NDL)
HFP = (DISCP_HFP × BPP)/(NDL × 8) – (2/NDL)
HBP = HBPplusHFP – HFP
(30)
7.6.4.2.5 Configure DSI_PHY
Calculate the timing in the functions of DDR_CLK_P (see
). In the example, DDR_CLK_P =
1000/DSI_DDR_CLK. See
, Clock Requirements, for details on timing calculation.
Table 7-91. Calculate DSI_PHY Timing
Steps
Registers
Value
Refer to
[31:24] REG_THSPREPARE
CEIL(70 ns/DDR clock period) + 2
ceil(175 ns/DDR clock period) + 2
REG_THSPRPR_THSZERO
[7:0] REG_THSEXIT
ceil(145 ns/DDR clock period)
[15:8] REG_THSTRAIL
ceil(60 ns/DDR clock period) + 5
[7:0] REG_TCLKPREPARE
ceil(65 ns/DDR clock period)
[7:0] REG_TCLKZERO
ceil(265 ns/DDR clock period)
[15:8] REG_TCLKTRAIL
ceil(60 ns/DDR clock period) + 2
[20:16] REG_TLPXBY2
ceil(25ns/DDR clock period)
NOTE:
Keep Reserved bits at reset value in the
and
registers.
7.6.4.2.6 Drive Stop State
lists the steps to Drive Stop State.
Table 7-92. Drive Stop State
Steps
Registers
Value
Force TX stop mode
[15] FORCE_TX_STOP_MODE_IO
0x1
Wait until FORCE_TX_STOP_MODE_IO = 0
[15] FORCE_TX_STOP_MODE_IO
Read 0x0
7.6.4.3
Initialization of the External MIPI Display Controller
1. Wait for the external MIPI display controller initialization after power up.
In this example, the external MIPI display controller is reset using GPIO 87.
2. Configure the external MIPI display controller.
1800
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated