TXBYTECLKHS
(O)
TXREQUESTHS
(I)
DP/DN
TXREADYHS
(O)
STOPSTATE
(O)
T
CLK-PREPARE
T
CLK-ZERO
T
LPX
T
CLK-TRAIL
T
HS-EXIT
HS CLK transmission
dss-185
Public Version
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Display Subsystem Basic Programming Model
•
DSS.
[29] RESETDONEPWRCLK bit: Reset done for the PWR clock domain.
The reset sequence of the PWR finite state-machine is complete when the RESETDONEPWRCLK
signal goes high.
7.5.6.3
Pad Configuration
The number of lanes is configurable through the DSS.
register.
It is not allowed to change on the fly the position (by modifying the DATAi_POSITION with i = 1 or 2 and
CLOCK_POSITION bit fields), P/N order (Positive/Negative order of the differential pair by modifying the
DATAi_POL with i = 1 or 2 and CLOCK_POL) or number of active data lanes (by modifying the
DSS.
[10:8] DATA2_POSITION bit). To add or remove the lane #2, it is required
to be in OFF mode for the DSI complex I/O.
The minimum requirement for the number of lanes is one clock lane and one data lane. Note that by
default, the data lane 2 is not connected (the DSS.
[10:8] DATA2_POSITION bit
reset value is 0).
7.5.6.4
Display Timing Configuration
NOTE:
Copyright © 2005-2008 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member
Confidential.
Depending on the CLKIN4DDR frequency settings programmed with the DSI PLL control module, software
users must program accordingly the timing parameters in the DSI complex I/O registers.
7.5.6.4.1 High-Speed Clock Transmission
shows an example of high-speed Clock Transmission.
Figure 7-140. High-Speed Clock Transmission
TXByteClkHS is an output clock which is derived by dividing CLKIN4DDR by 16.
1759
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated