dss-E124
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û
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ê
ê
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-
-
-
16
26
5*
_
Tdsif clk
8*
_
Thsbyte clk
Ttxclkesc
Tlp
_
available
LP_INTERLEAVING <
Public Version
Display Subsystem Functional Description
www.ti.com
ALLOWED_HSBYTE_CLOCKS_FOR_LP
=
BLANKING_PERIOD
–
(max{
ENTER_HS_MODE_LATENCY, 2} + 1)
•
Scenario 4: The gap for interleaving starts with the LP state and ends with a regular video stream HS
packet.
ALLOWED_HSBYTE_CLOCKS_FOR_LP = BLANKING_PERIOD – 1
After finishing Step 1, the time period available for LP interleaving is known:
T
lp_available
= ALLOWED_HSBYTE_CLOCKS_FOR_LP *T TxByteClkHS
Step 2:
The resulting value must be programmed in the appropriate video mode register for LP interleaving.
TxByteClkHS: Period of HS byte clock of DSI_PHY module
Tdsif_clk: Period of DSI functional clock
Ttxclkesc: Period of LP transmit escape clock
7.4.3.4
Power Management
The DSI protocol engine implements an handshake protocol on its L4 interconnect port with the PRCM.
The DSI protocol engine provides a clock gating signal CIO_CLK_ICG to gate the L3 interface clock
(L3_ICLK) provided by the PRCM to the DSI complex I/O. It allows reduction of the power consumption of
the DSI complex I/O while the DSI link is not in used. To gate the L3_ICLK clock at DSI complex I/O level,
set the DSS.
[14] CIO_CLK_ICG bit to 1.
7.4.3.5
Serial Configuration Port (SCP) Interface
The SCP interface is used to transfer register values from the DSI protocol engine to the DSI PLL Control
module and to the DSI complex I/O. It spends several cycles to serialize the data to be sent. Software
users must consider the delay in processing the transfer of the data from/to the slave port to/from the
module.
7.4.3.5.1 Shadowing Register
The two first SCP registers for the DSI complex I/O address map must be implemented as shadow
registers. The shadowing mechanism is enabled/disabled using the DSS.
SHADOWING bit:
•
When setting the DSS.
[31] SHADOWING bit to 1, the transfer of the values
from the two first L4 interconnect port registers into the two first registers of the DSI complex I/O
(DSS.
and DSS.
) is done only when the
DISPC_UPDATE_SYNC signal from the display controller is active and the
DSS.
[30] GOBIT is set to 1. If there is no pending update for the two
registers, when the DISPC_UPDATE_SYNC signal is asserted, the DSS.
[30]
GObit is reset by hardware and there is no SCP transfer.
–
If there is only one register to update, only the corresponding new value is transferred. The second
register in the DSI complex I/O is not updated. When the transfer is completed, the
DSS.
[30] GOBIT is reset by hardware.
–
If the two registers need to be updated, the order of the transfer is first the register with lower
address and then the second one. When the transfers are completed, the
DSS.
[30] GOBIT is reset by hardware.
When there is an on-going transfer (read or write) to any SCP register, the transfer must complete
before starting the update of shadowing registers.
•
When unsetting the DSS.
[31] SHADOWING bit to 0, if the transfer into the
1670
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
