Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1962 / 3738

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Display Subsystem Register Manual
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Table 7-453. Register Call Summary for Register DSI_PLL_CONFIGURATION1
Display Subsystem Functional Description
• DSI PLL Operations : [0] [1] [2]
Display Subsystem Basic Programming Model
• DSI PLL Lock Sequence : [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
• DSI PLL Recommended Values : [15]
Display Subsystem Use Cases and Tips
• Set Up DSI DPLL : [16] [17] [18] [19] [20]
• Configure DSI PLL : [21] [22] [23] [24] [25]
Display Subsystem Register Manual
• DSI PLL Controller Register Mapping Summary : [26]
Table 7-454. DSI_PLL_CONFIGURATION2
Address Offset 0x0000 0010
Physical Address 0x4804 FF10 Instance DSI_PLL_CTRL
Description This register contains the unlatched PLL and HSDIVDER configuration bits These bits are "shadowed"
when automatic mode is selected
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
DSI_PLL_IDLE
DSI_BYPASSEN
DSI_PLL_REFEN DSS_CLOCK_EN
DSI_PLL_CLKSEL
DSI_PHY_CLKINEN DSI_PLL_LOCKSEL
DSI_HSDIVBYPASS
DSS_CLOCK_PWDN
DSI_PLL_HIGHFREQ
DSI_PLL_PLLLPMODE
DSI_PROTO_CLOCK_EN
DSI_PLL_LOWCURRSTBY
DSI_PLL_DRIFTGUARDEN
DSI_PROTO_CLOCK_PWDN
DSI_PLL_TIGHTPHASELOCK
Bits Field Name Description Type Reset
31:21 RESERVED Reserved. Write only zero for future compatibility. Reads return R 0x000
zero.
20 DSI_HSDIVBYPASS Forces HSDIVIDER to bypass mode RW 0x0
0x0: HSDIVIDER in normal operation. Bypass controlled by PLL.
0x1: HSDIVIDER forced to bypass mode.
19 DSI_PROTO_CLOCK_ Power down for DSI Protocol Engine clock source RW 0x0
PWDN
0x0: DSI Protocol Engine clock divider is active
0x1: DSI Protocol Engine clock divider is powered-down
18 DSI_PROTO_CLOCK_ Enable for DSI Protocol Engine clock source RW 0x0
EN
0x0: DSI Protocol Engine clock divider is disabled
0x1: DSI Protocol Engine clock divider is enabled
17 DSS_CLOCK_PWDN Power down for DSS clock source RW 0x0
0x0: DSS clock divider is active
0x1: DSS clock divider is powered-down
16 DSS_CLOCK_EN Enable for DSS clock source RW 0x0
0x0: DSS clock divider is disabled
0x1: DSS clock divider is enabled
1962 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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