Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1755 / 3738

START
Select the pixel clock frequency
according to panel size
Select the DSI PLL clock source (CLKin)
(either SYS_CLK or PCLKFREE) by setting
the DSI_PLL_CONFIGURATION2[11]
DSI_PLL_CLKSEL bit
YES
NO
HSDIVIDER used ?
Set REGM3 factor such that
Set REGM factor such as
To reduce PLL lock time,
keep Fint high (around 2 MHz)
2 ( )
_ ( )
1 1
´
= ´
+ +
REGM CLKin MHz
DSI PHY MHz
REGN HIGHFREQ
DSI PLL will lock
Set the DSI_PLL_GO[0]
DSI_PLL_GO bit to 0b1
This sequence depends on the
selected mode:
automatic or manual
DSI_PLL_STATUS[1]
DSI_PLL_LOCK bit is set to 0b1 by HW
_ ( )
1_ _ ( )
3 1
=
+
DSI PHY MHz
DSI PLL FCLK MHz
REGM
Data Rate (Mbps) =
Pixel clock x Format
YES
NO
Clock frequency<32 MHz?
Set
DSI_PLL_CONFIGURATION2[12]
DSI_PLL_HIGHFREQ bit to 0
Set
bit to 1
DSI_PLL_CONFIGURATION2[12]
DSI_PLL_HIGHFREQ
Set REGN factor such that
Set REGN factor such that
( )
0 75 int 2 1
2 1
< = <
´ +
CLKin
. MHz F . MHz
REGN
0 75 int 2 1
1
< = <
+
CLKin
. MHz F . MHz
REGN
Set REGM4 factor such that
_ ( )
2 _ _ ( )
4 1
=
+
DSI PHY MHz
DSI PLL FCLK MHz
REGM
dss-190
CLKIN4DDR
CLKIN4DDR
CLKIN4DDR
Public Version
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Display Subsystem Basic Programming Model
• REGM factor is programed by DSS. DSI_PLL_CONFIGURATION1 [18:8] DSI_PLL_REGM bit field
• REGN factor is programed by DSS. DSI_PLL_CONFIGURATION1 [7:1] DSI_PLL_REGN bit field
• REGM3 factor is programed by DSS. DSI_PLL_CONFIGURATION1 [22:19] DSI_CLOCK_DIV bit field
• REGM4 factor is programed by DSS. DSI_PLL_CONFIGURATION1 [26:23] DSIPROTO_CLOCK_DIV
bit field
Figure 7-139 shows the programming sequence.
Figure 7-139. DSI PLL Programming Sequence
1755 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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