Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1961 / 3738

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Display Subsystem Register Manual
Bits Field Name Description Type Reset
31:1 RESERVED Reserved. Write only zero for future compatibility. Reads R 0x00000000
return zero.
0 DSI_PLL_GO Request (re-)locking sequence of the PLL. RW 0x0
If the AutoMode bit is set, then this will be deferred until
DISPC_UPDATE_SYNC goes active
0x0: No pending action
0x1: Request PLL (re-)locking/locking pending
Table 7-451. Register Call Summary for Register DSI_PLL_GO
Display Subsystem Basic Programming Model
• DSI PLL Go Sequence : [0] [1]
• DSI PLL Clock Gating Sequence : [2] [3]
• DSI PLL Recommended Values : [4]
Display Subsystem Use Cases and Tips
• Set Up DSI DPLL : [5] [6] [7] [8] [9]
• Configure DSI PLL : [10] [11] [12] [13] [14]
Display Subsystem Register Manual
• DSI PLL Controller Register Mapping Summary : [15]
• DSI PLL Control Module Registers : [16]
Table 7-452. DSI_PLL_CONFIGURATION1
Address Offset 0x0000 000C
Physical Address 0x4804 FF0C Instance DSI_PLL_CTRL
Description This register contains the latched PLL and HSDIVDER configuration bits
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DSI_PLL_REGM DSI_PLL_REGN
DSS_CLOCK_DIV
DSI_PLL_STOPMODE
DSIPROTO_CLOCK_DIV
Bits Field Name Description Type Reset
31:27 RESERVED Reserved. Write only zero for future compatibility. R 0x00
Reads return zero.
26:23 DSIPROTO_CLOCK_DIV Divider value for DSI Protocol Engine clock source RW 0x0
REGM4
22:19 DSS_CLOCK_DIV Divider value for DSS clock source RW 0x0
REGM3
18:8 DSI_PLL_REGM M Divider for PLL RW 0x000
7:1 DSI_PLL_REGN N Divider for PLL (Reference) RW 0x00
0 DSI_PLL_STOPMODE DSI PLL STOPMODE RW 0x0
0x0: STOPMODE is not selected
0x1: STOPMODE is selected
1961 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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