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Display Subsystem Basic Programming Model
7.5.5.6
DSI PLL Error Handling
The PLL lock and recalibration signals may be monitored to detect loss of lock or requirement to
recalibrate (due to large temperature change since the last lock request):
•
The DSS.
[1] DSI_PLL_LOCK status bit gives the DSI PLL lock state.
•
The DSS.
[2] DSI_PLL_RECAL status bit informs if the PLL must be uncalibrated
These signals can also generate interrupts at DSI protocol engine level:
•
DSS.
[9], PLL_RECAL_IRQ bit
•
DSS.
[8] PLL_UNLOCK_IRQ
•
DSS.
[7] PLL_LOCK_IRQ
The PLL_LOCK_IRQ interrupt indicates that the DSI PLL is locked. To monitor this event, read the
DSS.
[7] PLL_LOCK_IRQ bit. Set this bit to 1 to clear the status bit.
The PLL_UNLOCK_IRQ interrupt indicates that the DSI PLL is unlocked. To monitor this event, read the
DSS.
[8] PLL_UNLOCK_IRQ bit. Set this bit to 1 to clear the status bit.
The PLL_RECAL_IRQ interrupt indicates that the DSI PLL must be recalibrated. To monitor this event,
read the DSS.
[9] PLL_RECAL_IRQ bit. Set this bit to 1 to clear the status bit.
The PLL reference loss and limp status signals can also be monitored:
•
The DSS.
[3] DSI_PLL_LOSSREF status bit informs if the DSI PLL has lost the
reference.
•
The DSS.
[4] DSI_PLL_LIMP status bit informs about the DSI PLL limp status.
7.5.5.7
DSI PLL Recommended Values
shows the DSI PLL recommended values.
Table 7-68. Recommended Programming Values
Field Name
Value
Description
DSI_HSDIV_SYSRESET
0
Allow power FSM to control
DSI_PLL_SYSRESET
0
Allow power FSM to control
DSI_PLL_HALTMODE
-
See
for details
DSI_PLL_GATEMODE
-
See
for details
DSI_PLL_AUTOMODE
-
See
for details
1->0
Write a 1 when PLL is to be (re-)locked
with new parameters. This bit is cleared
by hardware when the PLL request has
completed
DSIPROTO_CLOCK_DIV
See
(1)
DSI protocol engine clock divider
DSS_CLOCK_DIV
See
(1)
DSS clock divider
DSI_PLL_REGM
See
(1)
Feedback clock divider
DSI_PLL_REGN
See
(1)
Reference clock divider
DSI_PLL_STOPMODE
1
Required to use GATEMODE bit
DSI_HSDIVBYPASS
0
PLL is controlling HSDIVIDER bypass
DSI_PROTO_CLOCK_PWDN
0
If PLL/HSDIVIDER is used as the DSI
protocol clock source
DSI_PROTO_CLOCK_EN
1
If PLL/HSDIVIDER is used as the DSI
protocol clock source
DSS_CLOCK_PWDN
0
If PLL/HSDIVIDER is used as the DSS
clock source
DSS_CLOCK_EN
1
If PLL/HSDIVIDER is used as the DSS
clock source
(1)
The bit field value must be set according to the desired clock frequency.
1757
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
