Automatic mode
Yes
DISPC_UPDATE_SYNC signal
asserted?
Yes
No
Update shadow register
Generate TINITZ, etc. sequence
Configuration signals
updated
PLL reprogrammed
Wait for PLL to relock
Synchronize to
DISPC vertical
blanking
Lock asserted ?
Yes
No
Completed
DSI_PLL_CONFIGURATION[13].DSI_PLL_REFEN bit set to 1
by software
DSI_PLL_GO[0].DSI_PLL_GO bit set to 1
Clear DSI_PLL_GO[0] DSI_PLL_GO bit to 0
dss-183
Clear
to 0
CLKINEN
Set HSDIVBYPASS to 1
BYPASSACKZ = 0?
No
Yes
Set CLKINEN to 1
Clear HSDIVBYPASS to 0
CLKIN4DDR clock runs
HSDIVIDER running
CLKIN4DDR clock stops
HSDIVIDER bypassed
PLL and HDIVIDER
in bypass
Public Version
www.ti.com
Display Subsystem Basic Programming Model
Figure 7-137. DSI PLL Go Sequence (Automatic Mode)
NOTE: All thick-outlined blocks show operations performed by software. Other blocks show operations performed
by hardware.
7.5.5.4
DSI PLL Clock Gating Sequence
Clock gating can be used to reduce system power consumption when the DSI protocol engine indicates
that it does not need the clock. If the HSDIVIDER is not used, the PLL can also be stopped (at the cost of
additional unstarting latency).
The DSI protocol engine can verify when the PLL has unstarted by inspecting the LOCK signal
(DSS.
[1] DSI_PLL_LOCK status bit). Because TxByteClkHS is stopped when the
CLKIN4DDR is stopped, this should obviate the need for any explicit feedback that the clock has been
unstarted in the other case. This flow chart should run even if the DSS.
[0]
bit
has not been set.
shows the DSI PLL gated mode sequence.
1753
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
