Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1960 / 3738

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
6 DSI_PLL_BYPASS DSI PLL Bypass status R 0x0
0x0: PLL not bypassing
0x1: PLL bypass
5 DSI_PLL_HIGHJITTER DSI PLL High Jitter status R 0x0
0x0: PLL in normal jitter condition
0x1: PLL in high jitter condition: Phase error > 24%
(TIGHTPHASELOCK = 0) Phase error > 12%
(TIGHTPHASELOCK = 1)
4 DSI_PLL_LIMP DSI PLL Limp status R 0x0
0x0: LIMP mode inactive
0x1: LIMP mode active
3 DSI_PLL_LOSSREF DSI PLL Reference Loss status R 0x0
0x0: Reference input active
0x1: Reference input inactive
2 DSI_PLL_RECAL DSI PLL re-calibration status R 0x0
If this bit is active, the PLL must be recalibrated
0x0: Recalibration is not required
0x1: Recalibration is required
1 DSI_PLL_LOCK DSI PLL Lock status R 0x0
See the programming guide for the use of this bit
0x0: PLL is not locked
0x1: PLL is locked
0 DSI_PLLCTRL_ DSI PLL Controller reset done status R 0x0
RESET_DONE
0x0: Reset is in progress
0x1: Reset has completed
Table 7-449. Register Call Summary for Register DSI_PLL_STATUS
Display Subsystem Functional Description
• Error Handling : [0] [1]
Display Subsystem Basic Programming Model
• Software Reset : [2]
• DSI PLL Clock Gating Sequence : [3]
• DSI PLL Error Handling : [4] [5] [6] [7]
Display Subsystem Use Cases and Tips
• Set Up DSI DPLL : [8]
• Configure DSI PLL : [9]
Display Subsystem Register Manual
• DSI PLL Controller Register Mapping Summary : [10]
Table 7-450. DSI_PLL_GO
Address Offset 0x0000 0008
Physical Address 0x4804 FF08 Instance DSI_PLL_CTRL
Description This register contains the GO bit
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
DSI_PLL_GO
1960 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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